1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Renesas RZ/A1 Interrupt Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chris Brandt <chris.brandt@renesas.com>
11*4882a593Smuzhiyun  - Geert Uytterhoeven <geert+renesas@glider.be>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
15*4882a593Smuzhiyun  RZ/A2 SoCs:
16*4882a593Smuzhiyun    - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17*4882a593Smuzhiyun    - NMI edge select.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunallOf:
20*4882a593Smuzhiyun  - $ref: /schemas/interrupt-controller.yaml#
21*4882a593Smuzhiyun
22*4882a593Smuzhiyunproperties:
23*4882a593Smuzhiyun  compatible:
24*4882a593Smuzhiyun    items:
25*4882a593Smuzhiyun      - enum:
26*4882a593Smuzhiyun          - renesas,r7s72100-irqc # RZ/A1H
27*4882a593Smuzhiyun          - renesas,r7s9210-irqc  # RZ/A2M
28*4882a593Smuzhiyun      - const: renesas,rza1-irqc
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  '#interrupt-cells':
31*4882a593Smuzhiyun    const: 2
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  '#address-cells':
34*4882a593Smuzhiyun    const: 0
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  interrupt-controller: true
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  reg:
39*4882a593Smuzhiyun    maxItems: 1
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  interrupt-map:
42*4882a593Smuzhiyun    maxItems: 8
43*4882a593Smuzhiyun    description: Specifies the mapping from external interrupts to GIC interrupts.
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  interrupt-map-mask:
46*4882a593Smuzhiyun    items:
47*4882a593Smuzhiyun      - const: 7
48*4882a593Smuzhiyun      - const: 0
49*4882a593Smuzhiyun
50*4882a593Smuzhiyunrequired:
51*4882a593Smuzhiyun  - compatible
52*4882a593Smuzhiyun  - '#interrupt-cells'
53*4882a593Smuzhiyun  - '#address-cells'
54*4882a593Smuzhiyun  - interrupt-controller
55*4882a593Smuzhiyun  - reg
56*4882a593Smuzhiyun  - interrupt-map
57*4882a593Smuzhiyun  - interrupt-map-mask
58*4882a593Smuzhiyun
59*4882a593SmuzhiyunadditionalProperties: false
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunexamples:
62*4882a593Smuzhiyun  - |
63*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
64*4882a593Smuzhiyun    irqc: interrupt-controller@fcfef800 {
65*4882a593Smuzhiyun            compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
66*4882a593Smuzhiyun            #interrupt-cells = <2>;
67*4882a593Smuzhiyun            #address-cells = <0>;
68*4882a593Smuzhiyun            interrupt-controller;
69*4882a593Smuzhiyun            reg = <0xfcfef800 0x6>;
70*4882a593Smuzhiyun            interrupt-map =
71*4882a593Smuzhiyun                    <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72*4882a593Smuzhiyun                    <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73*4882a593Smuzhiyun                    <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74*4882a593Smuzhiyun                    <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75*4882a593Smuzhiyun                    <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76*4882a593Smuzhiyun                    <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
77*4882a593Smuzhiyun                    <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78*4882a593Smuzhiyun                    <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
79*4882a593Smuzhiyun            interrupt-map-mask = <7 0>;
80*4882a593Smuzhiyun    };
81