xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Geert Uytterhoeven <geert+renesas@glider.be>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunproperties:
13*4882a593Smuzhiyun  compatible:
14*4882a593Smuzhiyun    items:
15*4882a593Smuzhiyun      - enum:
16*4882a593Smuzhiyun          - renesas,irqc-r8a73a4        # R-Mobile APE6
17*4882a593Smuzhiyun          - renesas,irqc-r8a7742        # RZ/G1H
18*4882a593Smuzhiyun          - renesas,irqc-r8a7743        # RZ/G1M
19*4882a593Smuzhiyun          - renesas,irqc-r8a7744        # RZ/G1N
20*4882a593Smuzhiyun          - renesas,irqc-r8a7745        # RZ/G1E
21*4882a593Smuzhiyun          - renesas,irqc-r8a77470       # RZ/G1C
22*4882a593Smuzhiyun          - renesas,irqc-r8a7790        # R-Car H2
23*4882a593Smuzhiyun          - renesas,irqc-r8a7791        # R-Car M2-W
24*4882a593Smuzhiyun          - renesas,irqc-r8a7792        # R-Car V2H
25*4882a593Smuzhiyun          - renesas,irqc-r8a7793        # R-Car M2-N
26*4882a593Smuzhiyun          - renesas,irqc-r8a7794        # R-Car E2
27*4882a593Smuzhiyun          - renesas,intc-ex-r8a774a1    # RZ/G2M
28*4882a593Smuzhiyun          - renesas,intc-ex-r8a774b1    # RZ/G2N
29*4882a593Smuzhiyun          - renesas,intc-ex-r8a774c0    # RZ/G2E
30*4882a593Smuzhiyun          - renesas,intc-ex-r8a7795     # R-Car H3
31*4882a593Smuzhiyun          - renesas,intc-ex-r8a7796     # R-Car M3-W
32*4882a593Smuzhiyun          - renesas,intc-ex-r8a77965    # R-Car M3-N
33*4882a593Smuzhiyun          - renesas,intc-ex-r8a77970    # R-Car V3M
34*4882a593Smuzhiyun          - renesas,intc-ex-r8a77980    # R-Car V3H
35*4882a593Smuzhiyun          - renesas,intc-ex-r8a77990    # R-Car E3
36*4882a593Smuzhiyun          - renesas,intc-ex-r8a77995    # R-Car D3
37*4882a593Smuzhiyun      - const: renesas,irqc
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  '#interrupt-cells':
40*4882a593Smuzhiyun    # an interrupt index and flags, as defined in interrupts.txt in
41*4882a593Smuzhiyun    # this directory
42*4882a593Smuzhiyun    const: 2
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  interrupt-controller: true
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  reg:
47*4882a593Smuzhiyun    maxItems: 1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  interrupts:
50*4882a593Smuzhiyun    minItems: 1
51*4882a593Smuzhiyun    maxItems: 32
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  clocks:
54*4882a593Smuzhiyun    maxItems: 1
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  power-domains:
57*4882a593Smuzhiyun    maxItems: 1
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun  resets:
60*4882a593Smuzhiyun    maxItems: 1
61*4882a593Smuzhiyun
62*4882a593Smuzhiyunrequired:
63*4882a593Smuzhiyun  - compatible
64*4882a593Smuzhiyun  - '#interrupt-cells'
65*4882a593Smuzhiyun  - interrupt-controller
66*4882a593Smuzhiyun  - reg
67*4882a593Smuzhiyun  - interrupts
68*4882a593Smuzhiyun  - clocks
69*4882a593Smuzhiyun
70*4882a593SmuzhiyunadditionalProperties: false
71*4882a593Smuzhiyun
72*4882a593Smuzhiyunexamples:
73*4882a593Smuzhiyun  - |
74*4882a593Smuzhiyun    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
75*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
76*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun    irqc0: interrupt-controller@e61c0000 {
79*4882a593Smuzhiyun        compatible = "renesas,irqc-r8a7790", "renesas,irqc";
80*4882a593Smuzhiyun        #interrupt-cells = <2>;
81*4882a593Smuzhiyun        interrupt-controller;
82*4882a593Smuzhiyun        reg = <0xe61c0000 0x200>;
83*4882a593Smuzhiyun        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
84*4882a593Smuzhiyun                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
85*4882a593Smuzhiyun                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
86*4882a593Smuzhiyun                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
87*4882a593Smuzhiyun        clocks = <&cpg CPG_MOD 407>;
88*4882a593Smuzhiyun    };
89