1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Renesas Interrupt Controller (INTC) for external pins
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Geert Uytterhoeven <geert+renesas@glider.be>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunproperties:
13*4882a593Smuzhiyun  compatible:
14*4882a593Smuzhiyun    items:
15*4882a593Smuzhiyun      - enum:
16*4882a593Smuzhiyun          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
17*4882a593Smuzhiyun          - renesas,intc-irqpin-r8a7778  # R-Car M1A
18*4882a593Smuzhiyun          - renesas,intc-irqpin-r8a7779  # R-Car H1
19*4882a593Smuzhiyun          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
20*4882a593Smuzhiyun      - const: renesas,intc-irqpin
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  reg:
23*4882a593Smuzhiyun    minItems: 5
24*4882a593Smuzhiyun    items:
25*4882a593Smuzhiyun      - description: Interrupt control register
26*4882a593Smuzhiyun      - description: Interrupt priority register
27*4882a593Smuzhiyun      - description: Interrupt source register
28*4882a593Smuzhiyun      - description: Interrupt mask register
29*4882a593Smuzhiyun      - description: Interrupt mask clear register
30*4882a593Smuzhiyun      - description: Interrupt control register for ICR0 with IRLM0 bit
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  interrupt-controller: true
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  '#interrupt-cells':
35*4882a593Smuzhiyun    const: 2
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  interrupts:
38*4882a593Smuzhiyun    minItems: 1
39*4882a593Smuzhiyun    maxItems: 8
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  sense-bitfield-width:
42*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
43*4882a593Smuzhiyun    enum: [2, 4]
44*4882a593Smuzhiyun    default: 4
45*4882a593Smuzhiyun    description:
46*4882a593Smuzhiyun      Width of a single sense bitfield in the SENSE register, if different from the
47*4882a593Smuzhiyun      default.
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  control-parent:
50*4882a593Smuzhiyun    type: boolean
51*4882a593Smuzhiyun    description:
52*4882a593Smuzhiyun      Disable and enable interrupts on the parent interrupt controller, needed for some
53*4882a593Smuzhiyun      broken implementations.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun  clocks:
56*4882a593Smuzhiyun    maxItems: 1
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun  power-domains:
59*4882a593Smuzhiyun    maxItems: 1
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunrequired:
62*4882a593Smuzhiyun  - compatible
63*4882a593Smuzhiyun  - reg
64*4882a593Smuzhiyun  - interrupt-controller
65*4882a593Smuzhiyun  - '#interrupt-cells'
66*4882a593Smuzhiyun  - interrupts
67*4882a593Smuzhiyun
68*4882a593Smuzhiyunif:
69*4882a593Smuzhiyun  properties:
70*4882a593Smuzhiyun    compatible:
71*4882a593Smuzhiyun      contains:
72*4882a593Smuzhiyun        enum:
73*4882a593Smuzhiyun          - renesas,intc-irqpin-r8a7740
74*4882a593Smuzhiyun          - renesas,intc-irqpin-sh73a0
75*4882a593Smuzhiyunthen:
76*4882a593Smuzhiyun  required:
77*4882a593Smuzhiyun    - clocks
78*4882a593Smuzhiyun    - power-domains
79*4882a593Smuzhiyun
80*4882a593SmuzhiyunadditionalProperties: false
81*4882a593Smuzhiyun
82*4882a593Smuzhiyunexamples:
83*4882a593Smuzhiyun  - |
84*4882a593Smuzhiyun    #include <dt-bindings/clock/r8a7740-clock.h>
85*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
86*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun    irqpin1: interrupt-controller@e6900004 {
89*4882a593Smuzhiyun        compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
90*4882a593Smuzhiyun        reg = <0xe6900004 4>,
91*4882a593Smuzhiyun              <0xe6900014 4>,
92*4882a593Smuzhiyun              <0xe6900024 1>,
93*4882a593Smuzhiyun              <0xe6900044 1>,
94*4882a593Smuzhiyun              <0xe6900064 1>;
95*4882a593Smuzhiyun        interrupt-controller;
96*4882a593Smuzhiyun        #interrupt-cells = <2>;
97*4882a593Smuzhiyun        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
98*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
99*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
100*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
101*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
102*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
103*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
104*4882a593Smuzhiyun                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
105*4882a593Smuzhiyun        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
106*4882a593Smuzhiyun        power-domains = <&pd_a4s>;
107*4882a593Smuzhiyun    };
108