1*4882a593SmuzhiyunPDC interrupt controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunQualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a 4*4882a593SmuzhiyunPower Domain Controller (PDC) that is on always-on domain. In addition to 5*4882a593Smuzhiyunproviding power control for the power domains, the hardware also has an 6*4882a593Smuzhiyuninterrupt controller that can be used to help detect edge low interrupts as 7*4882a593Smuzhiyunwell detect interrupts when the GIC is non-operational. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunGIC is parent interrupt controller at the highest level. Platform interrupt 10*4882a593Smuzhiyuncontroller PDC is next in hierarchy, followed by others. Drivers requiring 11*4882a593Smuzhiyunwakeup capabilities of their device interrupts routed through the PDC, must 12*4882a593Smuzhiyunspecify PDC as their interrupt controller and request the PDC port associated 13*4882a593Smuzhiyunwith the GIC interrupt. See example below. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunProperties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- compatible: 18*4882a593Smuzhiyun Usage: required 19*4882a593Smuzhiyun Value type: <string> 20*4882a593Smuzhiyun Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" 21*4882a593Smuzhiyun - "qcom,sc7180-pdc": For SC7180 22*4882a593Smuzhiyun - "qcom,sdm845-pdc": For SDM845 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- reg: 25*4882a593Smuzhiyun Usage: required 26*4882a593Smuzhiyun Value type: <prop-encoded-array> 27*4882a593Smuzhiyun Definition: Specifies the base physical address for PDC hardware. 28*4882a593Smuzhiyun Optionally, specify the PDC's GIC interface registers that 29*4882a593Smuzhiyun need to be configured for wakeup capable GPIOs routed to 30*4882a593Smuzhiyun the PDC. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- interrupt-cells: 33*4882a593Smuzhiyun Usage: required 34*4882a593Smuzhiyun Value type: <u32> 35*4882a593Smuzhiyun Definition: Specifies the number of cells needed to encode an interrupt 36*4882a593Smuzhiyun source. 37*4882a593Smuzhiyun Must be 2. 38*4882a593Smuzhiyun The first element of the tuple is the PDC pin for the 39*4882a593Smuzhiyun interrupt. 40*4882a593Smuzhiyun The second element is the trigger type. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- interrupt-controller: 43*4882a593Smuzhiyun Usage: required 44*4882a593Smuzhiyun Value type: <bool> 45*4882a593Smuzhiyun Definition: Identifies the node as an interrupt controller. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun- qcom,pdc-ranges: 48*4882a593Smuzhiyun Usage: required 49*4882a593Smuzhiyun Value type: <u32 array> 50*4882a593Smuzhiyun Definition: Specifies the PDC pin offset and the number of PDC ports. 51*4882a593Smuzhiyun The tuples indicates the valid mapping of valid PDC ports 52*4882a593Smuzhiyun and their hwirq mapping. 53*4882a593Smuzhiyun The first element of the tuple is the starting PDC port. 54*4882a593Smuzhiyun The second element is the GIC hwirq number for the PDC port. 55*4882a593Smuzhiyun The third element is the number of interrupts in sequence. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun- qcom,scm-spi-cfg: 58*4882a593Smuzhiyun Usage: optional 59*4882a593Smuzhiyun Value type: <bool> 60*4882a593Smuzhiyun Definition: Specifies if the SPI configuration registers have to be 61*4882a593Smuzhiyun written from the firmware. Sometimes the PDC interface 62*4882a593Smuzhiyun register to the GIC can only be written from the firmware. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunExample: 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun pdc: interrupt-controller@b220000 { 67*4882a593Smuzhiyun compatible = "qcom,sdm845-pdc"; 68*4882a593Smuzhiyun reg = <0 0x0b220000 0 0x30000>, <0 0x179900f0 0 0x60>; 69*4882a593Smuzhiyun qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; 70*4882a593Smuzhiyun #interrupt-cells = <2>; 71*4882a593Smuzhiyun interrupt-parent = <&intc>; 72*4882a593Smuzhiyun interrupt-controller; 73*4882a593Smuzhiyun qcom,scm-spi-cfg; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunDT binding of a device that wants to use the GIC SPI 514 as a wakeup 77*4882a593Smuzhiyuninterrupt, must do - 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun wake-device { 80*4882a593Smuzhiyun interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunIn this case interrupt 514 would be mapped to port 2 on the PDC as defined by 84*4882a593Smuzhiyunthe qcom,pdc-ranges property. 85