1*4882a593SmuzhiyunBinding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe MISC interrupt controller is a secondary controller for lower priority 4*4882a593Smuzhiyuninterrupt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or 8*4882a593Smuzhiyun "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" 9*4882a593Smuzhiyun- reg: Base address and size of the controllers memory area 10*4882a593Smuzhiyun- interrupts: Interrupt specifier for the controllers interrupt. 11*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 12*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode interrupt 13*4882a593Smuzhiyun source, should be 1 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunCompatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, 16*4882a593Smuzhiyunuse ar7240 for all other SoCs. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common 19*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupt-controller@18060010 { 24*4882a593Smuzhiyun compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; 25*4882a593Smuzhiyun reg = <0x18060010 0x4>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 28*4882a593Smuzhiyun interrupts = <6>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupt-controller; 31*4882a593Smuzhiyun #interrupt-cells = <1>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunAnother example: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupt-controller@18060010 { 37*4882a593Smuzhiyun compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; 38*4882a593Smuzhiyun reg = <0x18060010 0x4>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 41*4882a593Smuzhiyun interrupts = <6>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun interrupt-controller; 44*4882a593Smuzhiyun #interrupt-cells = <1>; 45*4882a593Smuzhiyun }; 46