1*4882a593SmuzhiyunBinding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunOn most SoC the IRQ controller need to flush the DDR FIFO before running
4*4882a593Smuzhiyunthe interrupt handler of some devices. This is configured using the
5*4882a593Smuzhiyunqca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired Properties:
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
10*4882a593Smuzhiyun  as fallback
11*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller
12*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode interrupt
13*4882a593Smuzhiyun		     source, should be 1 for intc
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common
16*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunOptional Properties:
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
21*4882a593Smuzhiyun  buffer flush
22*4882a593Smuzhiyun- qca,ddr-wb-channels: List of phandles to the write buffer channels for
23*4882a593Smuzhiyun  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
24*4882a593Smuzhiyun  default to the entry's index.
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunExample:
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	interrupt-controller {
29*4882a593Smuzhiyun		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		interrupt-controller;
32*4882a593Smuzhiyun		#interrupt-cells = <1>;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35*4882a593Smuzhiyun		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
36*4882a593Smuzhiyun					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	...
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	ddr_ctrl: memory-controller@18000000 {
42*4882a593Smuzhiyun		...
43*4882a593Smuzhiyun		#qca,ddr-wb-channel-cells = <1>;
44*4882a593Smuzhiyun	};
45