1*4882a593SmuzhiyunOpen Multi-Processor Interrupt Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : This should be "openrisc,ompic" 6*4882a593Smuzhiyun- reg : Specifies base physical address and size of the register space. The 7*4882a593Smuzhiyun size is based on the number of cores the controller has been configured 8*4882a593Smuzhiyun to handle, this should be set to 8 bytes per cpu core. 9*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller. 10*4882a593Smuzhiyun- #interrupt-cells : This should be set to 0 as this will not be an irq 11*4882a593Smuzhiyun parent. 12*4882a593Smuzhiyun- interrupts : Specifies the interrupt line to which the ompic is wired. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunompic: interrupt-controller@98000000 { 17*4882a593Smuzhiyun compatible = "openrisc,ompic"; 18*4882a593Smuzhiyun reg = <0x98000000 16>; 19*4882a593Smuzhiyun interrupt-controller; 20*4882a593Smuzhiyun #interrupt-cells = <0>; 21*4882a593Smuzhiyun interrupts = <1>; 22*4882a593Smuzhiyun}; 23