1*4882a593Smuzhiyun* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". 5*4882a593Smuzhiyun- reg: should contain IC registers location and length. 6*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller. 7*4882a593Smuzhiyun- #interrupt-cells: the number of cells to define an interrupt, should be 2. 8*4882a593Smuzhiyun The first cell is the IRQ number, the second cell is used to specify 9*4882a593Smuzhiyun one of the supported IRQ types: 10*4882a593Smuzhiyun IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, 11*4882a593Smuzhiyun IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, 12*4882a593Smuzhiyun IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, 13*4882a593Smuzhiyun IRQ_TYPE_LEVEL_LOW = active low level-sensitive. 14*4882a593Smuzhiyun Reset value is IRQ_TYPE_LEVEL_LOW. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun- interrupts: empty for MIC interrupt controller, cascaded MIC 18*4882a593Smuzhiyun hardware interrupts for SIC1 and SIC2 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExamples: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ 23*4882a593Smuzhiyun mic: interrupt-controller@40008000 { 24*4882a593Smuzhiyun compatible = "nxp,lpc3220-mic"; 25*4882a593Smuzhiyun reg = <0x40008000 0x4000>; 26*4882a593Smuzhiyun interrupt-controller; 27*4882a593Smuzhiyun #interrupt-cells = <2>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun sic1: interrupt-controller@4000c000 { 31*4882a593Smuzhiyun compatible = "nxp,lpc3220-sic"; 32*4882a593Smuzhiyun reg = <0x4000c000 0x4000>; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun #interrupt-cells = <2>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupt-parent = <&mic>; 37*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 38*4882a593Smuzhiyun <30 IRQ_TYPE_LEVEL_LOW>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun sic2: interrupt-controller@40010000 { 42*4882a593Smuzhiyun compatible = "nxp,lpc3220-sic"; 43*4882a593Smuzhiyun reg = <0x40010000 0x4000>; 44*4882a593Smuzhiyun interrupt-controller; 45*4882a593Smuzhiyun #interrupt-cells = <2>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interrupt-parent = <&mic>; 48*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 49*4882a593Smuzhiyun <31 IRQ_TYPE_LEVEL_LOW>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* ADC */ 53*4882a593Smuzhiyun adc@40048000 { 54*4882a593Smuzhiyun compatible = "nxp,lpc3220-adc"; 55*4882a593Smuzhiyun reg = <0x40048000 0x1000>; 56*4882a593Smuzhiyun interrupt-parent = <&sic1>; 57*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 58*4882a593Smuzhiyun }; 59