1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: MStar Interrupt Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Mark-PK Tsai <mark-pk.tsai@mediatek.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy 14*4882a593Smuzhiyun interrupt controllers that routes interrupts to the GIC. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun The HW block exposes a number of interrupt controllers, each 17*4882a593Smuzhiyun can support up to 64 interrupts. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: mstar,mst-intc 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupt-controller: true 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun "#interrupt-cells": 26*4882a593Smuzhiyun const: 3 27*4882a593Smuzhiyun description: | 28*4882a593Smuzhiyun Use the same format as specified by GIC in arm,gic.yaml. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun mstar,irqs-map-range: 34*4882a593Smuzhiyun description: | 35*4882a593Smuzhiyun The range <start, end> of parent interrupt controller's interrupt 36*4882a593Smuzhiyun lines that are hardwired to mstar interrupt controller. 37*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-matrix 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun minItems: 2 40*4882a593Smuzhiyun maxItems: 2 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun mstar,intc-no-eoi: 43*4882a593Smuzhiyun description: 44*4882a593Smuzhiyun Mark this controller has no End Of Interrupt(EOI) implementation. 45*4882a593Smuzhiyun type: boolean 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunrequired: 48*4882a593Smuzhiyun - compatible 49*4882a593Smuzhiyun - reg 50*4882a593Smuzhiyun - mstar,irqs-map-range 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunadditionalProperties: false 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunexamples: 55*4882a593Smuzhiyun - | 56*4882a593Smuzhiyun mst_intc0: interrupt-controller@1f2032d0 { 57*4882a593Smuzhiyun compatible = "mstar,mst-intc"; 58*4882a593Smuzhiyun interrupt-controller; 59*4882a593Smuzhiyun #interrupt-cells = <3>; 60*4882a593Smuzhiyun interrupt-parent = <&gic>; 61*4882a593Smuzhiyun reg = <0x1f2032d0 0x30>; 62*4882a593Smuzhiyun mstar,irqs-map-range = <0 63>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun... 65