1*4882a593SmuzhiyunMicrosemi Ocelot SoC ICPU Interrupt Controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun- compatible : should be "mscc,ocelot-icpu-intr"
6*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers.
7*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller
8*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode an
9*4882a593Smuzhiyun  interrupt source. The value shall be 1.
10*4882a593Smuzhiyun- interrupts : Specifies the CPU interrupt the controller is connected to.
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunExample:
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun		intc: interrupt-controller@70000070 {
15*4882a593Smuzhiyun			compatible = "mscc,ocelot-icpu-intr";
16*4882a593Smuzhiyun			reg = <0x70000070 0x70>;
17*4882a593Smuzhiyun			#interrupt-cells = <1>;
18*4882a593Smuzhiyun			interrupt-controller;
19*4882a593Smuzhiyun			interrupt-parent = <&cpuintc>;
20*4882a593Smuzhiyun			interrupts = <2>;
21*4882a593Smuzhiyun		};
22