xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Marvell MMP/Orion Interrupt controller bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Thomas Gleixner <tglx@linutronix.de>
11*4882a593Smuzhiyun  - Jason Cooper <jason@lakedaemon.net>
12*4882a593Smuzhiyun  - Marc Zyngier <maz@kernel.org>
13*4882a593Smuzhiyun  - Rob Herring <robh+dt@kernel.org>
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunallOf:
16*4882a593Smuzhiyun  - if:
17*4882a593Smuzhiyun      properties:
18*4882a593Smuzhiyun        compatible:
19*4882a593Smuzhiyun          not:
20*4882a593Smuzhiyun            contains:
21*4882a593Smuzhiyun              const: marvell,orion-intc
22*4882a593Smuzhiyun    then:
23*4882a593Smuzhiyun      required:
24*4882a593Smuzhiyun        - mrvl,intc-nr-irqs
25*4882a593Smuzhiyun  - if:
26*4882a593Smuzhiyun      properties:
27*4882a593Smuzhiyun        compatible:
28*4882a593Smuzhiyun          contains:
29*4882a593Smuzhiyun            enum:
30*4882a593Smuzhiyun              - mrvl,mmp-intc
31*4882a593Smuzhiyun              - mrvl,mmp2-intc
32*4882a593Smuzhiyun    then:
33*4882a593Smuzhiyun      properties:
34*4882a593Smuzhiyun        reg:
35*4882a593Smuzhiyun          maxItems: 1
36*4882a593Smuzhiyun  - if:
37*4882a593Smuzhiyun      properties:
38*4882a593Smuzhiyun        compatible:
39*4882a593Smuzhiyun          contains:
40*4882a593Smuzhiyun            enum:
41*4882a593Smuzhiyun              - marvell,mmp3-intc
42*4882a593Smuzhiyun              - mrvl,mmp2-mux-intc
43*4882a593Smuzhiyun    then:
44*4882a593Smuzhiyun      properties:
45*4882a593Smuzhiyun        reg:
46*4882a593Smuzhiyun          minItems: 2
47*4882a593Smuzhiyun  - if:
48*4882a593Smuzhiyun      properties:
49*4882a593Smuzhiyun        compatible:
50*4882a593Smuzhiyun          contains:
51*4882a593Smuzhiyun            const: mrvl,mmp2-mux-intc
52*4882a593Smuzhiyun    then:
53*4882a593Smuzhiyun      properties:
54*4882a593Smuzhiyun        interrupts:
55*4882a593Smuzhiyun          maxItems: 1
56*4882a593Smuzhiyun        reg-names:
57*4882a593Smuzhiyun          items:
58*4882a593Smuzhiyun            - const: 'mux status'
59*4882a593Smuzhiyun            - const: 'mux mask'
60*4882a593Smuzhiyun      required:
61*4882a593Smuzhiyun        - interrupts
62*4882a593Smuzhiyun    else:
63*4882a593Smuzhiyun      properties:
64*4882a593Smuzhiyun        interrupts: false
65*4882a593Smuzhiyun
66*4882a593Smuzhiyunproperties:
67*4882a593Smuzhiyun  '#interrupt-cells':
68*4882a593Smuzhiyun    const: 1
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun  compatible:
71*4882a593Smuzhiyun    enum:
72*4882a593Smuzhiyun      - mrvl,mmp-intc
73*4882a593Smuzhiyun      - mrvl,mmp2-intc
74*4882a593Smuzhiyun      - marvell,mmp3-intc
75*4882a593Smuzhiyun      - marvell,orion-intc
76*4882a593Smuzhiyun      - mrvl,mmp2-mux-intc
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun  reg:
79*4882a593Smuzhiyun    minItems: 1
80*4882a593Smuzhiyun    maxItems: 2
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun  reg-names: true
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun  interrupts: true
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun  interrupt-controller: true
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun  mrvl,intc-nr-irqs:
89*4882a593Smuzhiyun    description: |
90*4882a593Smuzhiyun      Specifies the number of interrupts in the interrupt controller.
91*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun  mrvl,clr-mfp-irq:
94*4882a593Smuzhiyun    description: |
95*4882a593Smuzhiyun      Specifies the interrupt that needs to clear MFP edge detection first.
96*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
97*4882a593Smuzhiyun
98*4882a593Smuzhiyunrequired:
99*4882a593Smuzhiyun  - '#interrupt-cells'
100*4882a593Smuzhiyun  - compatible
101*4882a593Smuzhiyun  - reg
102*4882a593Smuzhiyun  - interrupt-controller
103*4882a593Smuzhiyun
104*4882a593SmuzhiyunadditionalProperties: false
105*4882a593Smuzhiyun
106*4882a593Smuzhiyunexamples:
107*4882a593Smuzhiyun  - |
108*4882a593Smuzhiyun    interrupt-controller@d4282000 {
109*4882a593Smuzhiyun        compatible = "mrvl,mmp2-intc";
110*4882a593Smuzhiyun        interrupt-controller;
111*4882a593Smuzhiyun        #interrupt-cells = <1>;
112*4882a593Smuzhiyun        reg = <0xd4282000 0x1000>;
113*4882a593Smuzhiyun        mrvl,intc-nr-irqs = <64>;
114*4882a593Smuzhiyun    };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun    interrupt-controller@d4282150 {
117*4882a593Smuzhiyun        compatible = "mrvl,mmp2-mux-intc";
118*4882a593Smuzhiyun        interrupts = <4>;
119*4882a593Smuzhiyun        interrupt-controller;
120*4882a593Smuzhiyun        #interrupt-cells = <1>;
121*4882a593Smuzhiyun        reg = <0x150 0x4>, <0x168 0x4>;
122*4882a593Smuzhiyun        reg-names = "mux status", "mux mask";
123*4882a593Smuzhiyun        mrvl,intc-nr-irqs = <2>;
124*4882a593Smuzhiyun    };
125*4882a593Smuzhiyun  - |
126*4882a593Smuzhiyun    interrupt-controller@fed20204 {
127*4882a593Smuzhiyun        compatible = "marvell,orion-intc";
128*4882a593Smuzhiyun        interrupt-controller;
129*4882a593Smuzhiyun        #interrupt-cells = <1>;
130*4882a593Smuzhiyun        reg = <0xfed20204 0x04>,
131*4882a593Smuzhiyun              <0xfed20214 0x04>;
132*4882a593Smuzhiyun    };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun...
135