1*4882a593SmuzhiyunMicrochip PIC32 Interrupt Controller
2*4882a593Smuzhiyun====================================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThe Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
5*4882a593SmuzhiyunIt handles all internal and external interrupts. This controller exists outside
6*4882a593Smuzhiyunof the CPU and is the arbitrator of all interrupts (including interrupts from
7*4882a593Smuzhiyunthe CPU itself) before they are presented to the CPU.
8*4882a593Smuzhiyun
9*4882a593SmuzhiyunExternal interrupts have a software configurable edge polarity. Non external
10*4882a593Smuzhiyuninterrupts have a type and polarity that is determined by the source of the
11*4882a593Smuzhiyuninterrupt.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunRequired properties
14*4882a593Smuzhiyun-------------------
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun- compatible: Should be "microchip,pic32mzda-evic"
17*4882a593Smuzhiyun- reg: Specifies physical base address and size of register range.
18*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller.
19*4882a593Smuzhiyun- #interrupt cells: Specifies the number of cells used to encode an interrupt
20*4882a593Smuzhiyun  source connected to this controller. The value shall be 2 and interrupt
21*4882a593Smuzhiyun  descriptor shall have the following format:
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	<hw_irq irq_type>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  hw_irq - represents the hardware interrupt number as in the data sheet.
26*4882a593Smuzhiyun  irq_type - is used to describe the type and polarity of an interrupt. For
27*4882a593Smuzhiyun  internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
28*4882a593Smuzhiyun  IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
29*4882a593Smuzhiyun  IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunOptional properties
32*4882a593Smuzhiyun-------------------
33*4882a593Smuzhiyun- microchip,external-irqs: u32 array of external interrupts with software
34*4882a593Smuzhiyun  polarity configuration. This array corresponds to the bits in the INTCON
35*4882a593Smuzhiyun  SFR.
36*4882a593Smuzhiyun
37*4882a593SmuzhiyunExample
38*4882a593Smuzhiyun-------
39*4882a593Smuzhiyun
40*4882a593Smuzhiyunevic: interrupt-controller@1f810000 {
41*4882a593Smuzhiyun	compatible = "microchip,pic32mzda-evic";
42*4882a593Smuzhiyun	interrupt-controller;
43*4882a593Smuzhiyun	#interrupt-cells = <2>;
44*4882a593Smuzhiyun	reg = <0x1f810000 0x1000>;
45*4882a593Smuzhiyun	microchip,external-irqs = <3 8 13 18 23>;
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593SmuzhiyunEach device/peripheral must request its interrupt line with the associated type
49*4882a593Smuzhiyunand polarity.
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunInternal interrupt DTS snippet
52*4882a593Smuzhiyun------------------------------
53*4882a593Smuzhiyun
54*4882a593Smuzhiyundevice@1f800000 {
55*4882a593Smuzhiyun	...
56*4882a593Smuzhiyun	interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
57*4882a593Smuzhiyun	...
58*4882a593Smuzhiyun};
59*4882a593Smuzhiyun
60*4882a593SmuzhiyunExternal interrupt DTS snippet
61*4882a593Smuzhiyun------------------------------
62*4882a593Smuzhiyun
63*4882a593Smuzhiyundevice@1f800000 {
64*4882a593Smuzhiyun	...
65*4882a593Smuzhiyun	interrupts = <3 IRQ_TYPE_EDGE_RISING>;
66*4882a593Smuzhiyun	...
67*4882a593Smuzhiyun};
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