1*4882a593SmuzhiyunMarvell SEI (System Error Interrupt) Controller 2*4882a593Smuzhiyun----------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunMarvell SEI (System Error Interrupt) controller is an interrupt 5*4882a593Smuzhiyunaggregator. It receives interrupts from several sources and aggregates 6*4882a593Smuzhiyunthem to a single interrupt line (an SPI) on the parent interrupt 7*4882a593Smuzhiyuncontroller. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThis interrupt controller can handle up to 64 SEIs, a set comes from the 10*4882a593SmuzhiyunAP and is wired while a second set comes from the CPs by the mean of 11*4882a593SmuzhiyunMSIs. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- compatible: should be one of: 16*4882a593Smuzhiyun * "marvell,ap806-sei" 17*4882a593Smuzhiyun- reg: SEI registers location and length. 18*4882a593Smuzhiyun- interrupts: identifies the parent IRQ that will be triggered. 19*4882a593Smuzhiyun- #interrupt-cells: number of cells to define an SEI wired interrupt 20*4882a593Smuzhiyun coming from the AP, should be 1. The cell is the IRQ 21*4882a593Smuzhiyun number. 22*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 23*4882a593Smuzhiyun for AP interrupts. 24*4882a593Smuzhiyun- msi-controller: identifies the node as an MSI controller for the CPs 25*4882a593Smuzhiyun interrupts. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun sei: interrupt-controller@3f0200 { 30*4882a593Smuzhiyun compatible = "marvell,ap806-sei"; 31*4882a593Smuzhiyun reg = <0x3f0200 0x40>; 32*4882a593Smuzhiyun interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 33*4882a593Smuzhiyun #interrupt-cells = <1>; 34*4882a593Smuzhiyun interrupt-controller; 35*4882a593Smuzhiyun msi-controller; 36*4882a593Smuzhiyun }; 37