1*4882a593SmuzhiyunMarvell Orion SoC interrupt controllers 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun* Main interrupt controller 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: shall be "marvell,orion-intc" 7*4882a593Smuzhiyun- reg: base address(es) of interrupt registers starting with CAUSE register 8*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 9*4882a593Smuzhiyun- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe interrupt sources map to the corresponding bits in the interrupt 12*4882a593Smuzhiyunregisters, i.e. 13*4882a593Smuzhiyun- 0 maps to bit 0 of first base address, 14*4882a593Smuzhiyun- 1 maps to bit 1 of first base address, 15*4882a593Smuzhiyun- 32 maps to bit 0 of second base address, and so on. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun intc: interrupt-controller { 19*4882a593Smuzhiyun compatible = "marvell,orion-intc"; 20*4882a593Smuzhiyun interrupt-controller; 21*4882a593Smuzhiyun #interrupt-cells = <1>; 22*4882a593Smuzhiyun /* Dove has 64 first level interrupts */ 23*4882a593Smuzhiyun reg = <0x20200 0x10>, <0x20210 0x10>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun* Bridge interrupt controller 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunRequired properties: 29*4882a593Smuzhiyun- compatible: shall be "marvell,orion-bridge-intc" 30*4882a593Smuzhiyun- reg: base address of bridge interrupt registers starting with CAUSE register 31*4882a593Smuzhiyun- interrupts: bridge interrupt of the main interrupt controller 32*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 33*4882a593Smuzhiyun- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties: 36*4882a593Smuzhiyun- marvell,#interrupts: number of interrupts provided by bridge interrupt 37*4882a593Smuzhiyun controller, defaults to 32 if not set 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample: 40*4882a593Smuzhiyun bridge_intc: interrupt-controller { 41*4882a593Smuzhiyun compatible = "marvell,orion-bridge-intc"; 42*4882a593Smuzhiyun interrupt-controller; 43*4882a593Smuzhiyun #interrupt-cells = <1>; 44*4882a593Smuzhiyun reg = <0x20110 0x8>; 45*4882a593Smuzhiyun interrupts = <0>; 46*4882a593Smuzhiyun /* Dove bridge provides 5 interrupts */ 47*4882a593Smuzhiyun marvell,#interrupts = <5>; 48*4882a593Smuzhiyun }; 49