1*4882a593SmuzhiyunMarvell Armada 7K/8K PIC Interrupt controller
2*4882a593Smuzhiyun---------------------------------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThis is the Device Tree binding for the PIC, a secondary interrupt
5*4882a593Smuzhiyuncontroller available on the Marvell Armada 7K/8K ARM64 SoCs, and
6*4882a593Smuzhiyuntypically connected to the GIC as the primary interrupt controller.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunRequired properties:
9*4882a593Smuzhiyun- compatible: should be "marvell,armada-8k-pic"
10*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller
11*4882a593Smuzhiyun- #interrupt-cells: the number of cells to define interrupts on this
12*4882a593Smuzhiyun  controller. Should be 1
13*4882a593Smuzhiyun- reg: the register area for the PIC interrupt controller
14*4882a593Smuzhiyun- interrupts: the interrupt to the primary interrupt controller,
15*4882a593Smuzhiyun  typically the GIC
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunExample:
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	pic: interrupt-controller@3f0100 {
20*4882a593Smuzhiyun		compatible = "marvell,armada-8k-pic";
21*4882a593Smuzhiyun		reg = <0x3f0100 0x10>;
22*4882a593Smuzhiyun		#interrupt-cells = <1>;
23*4882a593Smuzhiyun		interrupt-controller;
24*4882a593Smuzhiyun		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
25*4882a593Smuzhiyun	};
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