1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Loongson Local I/O Interrupt Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Jiaxun Yang <jiaxun.yang@flygoat.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  This interrupt controller is found in the Loongson-3 family of chips as the primary
14*4882a593Smuzhiyun  package interrupt controller which can route local I/O interrupt to interrupt lines
15*4882a593Smuzhiyun  of cores.
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunallOf:
18*4882a593Smuzhiyun  - $ref: /schemas/interrupt-controller.yaml#
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  compatible:
22*4882a593Smuzhiyun    oneOf:
23*4882a593Smuzhiyun      - const: loongson,liointc-1.0
24*4882a593Smuzhiyun      - const: loongson,liointc-1.0a
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  reg:
27*4882a593Smuzhiyun    maxItems: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  interrupt-controller: true
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  interrupts:
32*4882a593Smuzhiyun    description:
33*4882a593Smuzhiyun      Interrupt source of the CPU interrupts.
34*4882a593Smuzhiyun    minItems: 1
35*4882a593Smuzhiyun    maxItems: 4
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  interrupt-names:
38*4882a593Smuzhiyun    description: List of names for the parent interrupts.
39*4882a593Smuzhiyun    items:
40*4882a593Smuzhiyun      - const: int0
41*4882a593Smuzhiyun      - const: int1
42*4882a593Smuzhiyun      - const: int2
43*4882a593Smuzhiyun      - const: int3
44*4882a593Smuzhiyun    minItems: 1
45*4882a593Smuzhiyun    maxItems: 4
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun  '#interrupt-cells':
48*4882a593Smuzhiyun    const: 2
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  'loongson,parent_int_map':
51*4882a593Smuzhiyun    description: |
52*4882a593Smuzhiyun      This property points how the children interrupts will be mapped into CPU
53*4882a593Smuzhiyun      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
54*4882a593Smuzhiyun      and each bit in the cell refers to a child interrupt from 0 to 31.
55*4882a593Smuzhiyun      If a CPU interrupt line didn't connect with liointc, then keep its
56*4882a593Smuzhiyun      cell with zero.
57*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32-array
58*4882a593Smuzhiyun    minItems: 4
59*4882a593Smuzhiyun    maxItems: 4
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunrequired:
62*4882a593Smuzhiyun  - compatible
63*4882a593Smuzhiyun  - reg
64*4882a593Smuzhiyun  - interrupts
65*4882a593Smuzhiyun  - interrupt-controller
66*4882a593Smuzhiyun  - '#interrupt-cells'
67*4882a593Smuzhiyun  - 'loongson,parent_int_map'
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun
70*4882a593SmuzhiyununevaluatedProperties: false
71*4882a593Smuzhiyun
72*4882a593Smuzhiyunexamples:
73*4882a593Smuzhiyun  - |
74*4882a593Smuzhiyun    iointc: interrupt-controller@3ff01400 {
75*4882a593Smuzhiyun      compatible = "loongson,liointc-1.0";
76*4882a593Smuzhiyun      reg = <0x3ff01400 0x64>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun      interrupt-controller;
79*4882a593Smuzhiyun      #interrupt-cells = <2>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun      interrupt-parent = <&cpuintc>;
82*4882a593Smuzhiyun      interrupts = <2>, <3>;
83*4882a593Smuzhiyun      interrupt-names = "int0", "int1";
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
86*4882a593Smuzhiyun                                <0x0f000000>, /* int1 */
87*4882a593Smuzhiyun                                <0x00000000>, /* int2 */
88*4882a593Smuzhiyun                                <0x00000000>; /* int3 */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun    };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun...
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