1*4882a593SmuzhiyunInterrupt chips
2*4882a593Smuzhiyun---------------
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun  Required properties:
7*4882a593Smuzhiyun  --------------------
8*4882a593Smuzhiyun     compatible = "intel,ce4100-ioapic";
9*4882a593Smuzhiyun     #interrupt-cells = <2>;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun  Device's interrupt property:
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun     interrupts = <P S>;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun  The first number (P) represents the interrupt pin which is wired to the
16*4882a593Smuzhiyun  IO APIC. The second number (S) represents the sense of interrupt which
17*4882a593Smuzhiyun  should be configured and can be one of:
18*4882a593Smuzhiyun    0 - Edge Rising
19*4882a593Smuzhiyun    1 - Level Low
20*4882a593Smuzhiyun    2 - Level High
21*4882a593Smuzhiyun    3 - Edge Falling
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun* Local APIC
24*4882a593Smuzhiyun  Required property:
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun     compatible = "intel,ce4100-lapic";
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