1*4882a593SmuzhiyunHisilicon mbigen device tree bindings. 2*4882a593Smuzhiyun======================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunMbigen means: message based interrupt generator. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunMBI is kind of msi interrupt only used on Non-PCI devices. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunTo reduce the wired interrupt number connected to GIC, 9*4882a593SmuzhiyunHisilicon designed mbigen to collect and generate interrupt. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunNon-pci devices can connect to mbigen and generate the 13*4882a593Smuzhiyuninterrupt by writing ITS register. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe mbigen chip and devices connect to mbigen have the following properties: 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunMbigen main node required properties: 18*4882a593Smuzhiyun------------------------------------------- 19*4882a593Smuzhiyun- compatible: Should be "hisilicon,mbigen-v2" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- reg: Specifies the base physical address and size of the Mbigen 22*4882a593Smuzhiyun registers. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunMbigen sub node required properties: 25*4882a593Smuzhiyun------------------------------------------ 26*4882a593Smuzhiyun- interrupt controller: Identifies the node as an interrupt controller 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- msi-parent: Specifies the MSI controller this mbigen use. 29*4882a593Smuzhiyun For more detail information,please refer to the generic msi-parent binding in 30*4882a593Smuzhiyun Documentation/devicetree/bindings/interrupt-controller/msi.txt. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- num-pins: the total number of pins implemented in this Mbigen 33*4882a593Smuzhiyun instance. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode an 36*4882a593Smuzhiyun interrupt source. The value must be 2. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun The 1st cell is hardware pin number of the interrupt.This number is local to 39*4882a593Smuzhiyun each mbigen chip and in the range from 0 to the maximum interrupts number 40*4882a593Smuzhiyun of the mbigen. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun The 2nd cell is the interrupt trigger type. 43*4882a593Smuzhiyun The value of this cell should be: 44*4882a593Smuzhiyun 1: rising edge triggered 45*4882a593Smuzhiyun or 46*4882a593Smuzhiyun 4: high level triggered 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunExamples: 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun mbigen_chip_dsa { 51*4882a593Smuzhiyun compatible = "hisilicon,mbigen-v2"; 52*4882a593Smuzhiyun reg = <0x0 0xc0080000 0x0 0x10000>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun mbigen_gmac:intc_gmac { 55*4882a593Smuzhiyun interrupt-controller; 56*4882a593Smuzhiyun msi-parent = <&its_dsa 0x40b1c>; 57*4882a593Smuzhiyun num-pins = <9>; 58*4882a593Smuzhiyun #interrupt-cells = <2>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun mbigen_i2c:intc_i2c { 62*4882a593Smuzhiyun interrupt-controller; 63*4882a593Smuzhiyun msi-parent = <&its_dsa 0x40b0e>; 64*4882a593Smuzhiyun num-pins = <2>; 65*4882a593Smuzhiyun #interrupt-cells = <2>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunDevices connect to mbigen required properties: 70*4882a593Smuzhiyun---------------------------------------------------- 71*4882a593Smuzhiyun-interrupts:Specifies the interrupt source. 72*4882a593Smuzhiyun For the specific information of each cell in this property,please refer to 73*4882a593Smuzhiyun the "interrupt-cells" description mentioned above. 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunExamples: 76*4882a593Smuzhiyun gmac0: ethernet@c2080000 { 77*4882a593Smuzhiyun #address-cells = <1>; 78*4882a593Smuzhiyun #size-cells = <0>; 79*4882a593Smuzhiyun reg = <0 0xc2080000 0 0x20000>, 80*4882a593Smuzhiyun <0 0xc0000000 0 0x1000>; 81*4882a593Smuzhiyun interrupt-parent = <&mbigen_device_gmac>; 82*4882a593Smuzhiyun interrupts = <656 1>, 83*4882a593Smuzhiyun <657 1>; 84*4882a593Smuzhiyun }; 85