1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale INTMUX interrupt multiplexer 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Joakim Zhang <qiangqing.zhang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun const: fsl,imx-intmux 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg: 17*4882a593Smuzhiyun maxItems: 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun interrupts: 20*4882a593Smuzhiyun minItems: 1 21*4882a593Smuzhiyun maxItems: 8 22*4882a593Smuzhiyun description: | 23*4882a593Smuzhiyun Should contain the parent interrupt lines (up to 8) used to multiplex 24*4882a593Smuzhiyun the input interrupts. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupt-controller: true 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun '#interrupt-cells': 29*4882a593Smuzhiyun const: 2 30*4882a593Smuzhiyun description: | 31*4882a593Smuzhiyun The 1st cell is hw interrupt number, the 2nd cell is channel index. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun description: ipg clock. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun const: ipg 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunrequired: 40*4882a593Smuzhiyun - compatible 41*4882a593Smuzhiyun - reg 42*4882a593Smuzhiyun - interrupts 43*4882a593Smuzhiyun - interrupt-controller 44*4882a593Smuzhiyun - '#interrupt-cells' 45*4882a593Smuzhiyun - clocks 46*4882a593Smuzhiyun - clock-names 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun interrupt-controller@37400000 { 53*4882a593Smuzhiyun compatible = "fsl,imx-intmux"; 54*4882a593Smuzhiyun reg = <0x37400000 0x1000>; 55*4882a593Smuzhiyun interrupts = <0 16 4>, 56*4882a593Smuzhiyun <0 17 4>, 57*4882a593Smuzhiyun <0 18 4>, 58*4882a593Smuzhiyun <0 19 4>, 59*4882a593Smuzhiyun <0 20 4>, 60*4882a593Smuzhiyun <0 21 4>, 61*4882a593Smuzhiyun <0 22 4>, 62*4882a593Smuzhiyun <0 23 4>; 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun interrupt-parent = <&gic>; 65*4882a593Smuzhiyun #interrupt-cells = <2>; 66*4882a593Smuzhiyun clocks = <&clk>; 67*4882a593Smuzhiyun clock-names = "ipg"; 68*4882a593Smuzhiyun }; 69