1*4882a593SmuzhiyunCirrus Logic CLPS711X Interrupt Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: Should be "cirrus,ep7209-intc". 6*4882a593Smuzhiyun- reg: Specifies base physical address of the registers set. 7*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller. 8*4882a593Smuzhiyun- #interrupt-cells: Specifies the number of cells needed to encode an 9*4882a593Smuzhiyun interrupt source. The value shall be 1. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe interrupt sources are as follows: 12*4882a593SmuzhiyunID Name Description 13*4882a593Smuzhiyun--------------------------- 14*4882a593Smuzhiyun1: BLINT Battery low (FIQ) 15*4882a593Smuzhiyun3: MCINT Media changed (FIQ) 16*4882a593Smuzhiyun4: CSINT CODEC sound 17*4882a593Smuzhiyun5: EINT1 External 1 18*4882a593Smuzhiyun6: EINT2 External 2 19*4882a593Smuzhiyun7: EINT3 External 3 20*4882a593Smuzhiyun8: TC1OI TC1 under flow 21*4882a593Smuzhiyun9: TC2OI TC2 under flow 22*4882a593Smuzhiyun10: RTCMI RTC compare match 23*4882a593Smuzhiyun11: TINT 64Hz tick 24*4882a593Smuzhiyun12: UTXINT1 UART1 transmit FIFO half empty 25*4882a593Smuzhiyun13: URXINT1 UART1 receive FIFO half full 26*4882a593Smuzhiyun14: UMSINT UART1 modem status changed 27*4882a593Smuzhiyun15: SSEOTI SSI1 end of transfer 28*4882a593Smuzhiyun16: KBDINT Keyboard 29*4882a593Smuzhiyun17: SS2RX SSI2 receive FIFO half or greater full 30*4882a593Smuzhiyun18: SS2TX SSI2 transmit FIFO less than half empty 31*4882a593Smuzhiyun28: UTXINT2 UART2 transmit FIFO half empty 32*4882a593Smuzhiyun29: URXINT2 UART2 receive FIFO half full 33*4882a593Smuzhiyun32: DAIINT DAI interface (FIQ) 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunExample: 36*4882a593Smuzhiyun intc: interrupt-controller { 37*4882a593Smuzhiyun compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; 38*4882a593Smuzhiyun reg = <0x80000000 0x4000>; 39*4882a593Smuzhiyun interrupt-controller; 40*4882a593Smuzhiyun #interrupt-cells = <1>; 41*4882a593Smuzhiyun }; 42