1*4882a593SmuzhiyunBroadcom Generic Level 2 Interrupt Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: should be one of: 6*4882a593Smuzhiyun "brcm,hif-spi-l2-intc" or 7*4882a593Smuzhiyun "brcm,upg-aux-aon-l2-intc" or 8*4882a593Smuzhiyun "brcm,l2-intc" for latched interrupt controllers 9*4882a593Smuzhiyun should be "brcm,bcm7271-l2-intc" for level interrupt controllers 10*4882a593Smuzhiyun- reg: specifies the base physical address and size of the registers 11*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 12*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an 13*4882a593Smuzhiyun interrupt source. Should be 1. 14*4882a593Smuzhiyun- interrupts: specifies the interrupt line in the interrupt-parent irq space 15*4882a593Smuzhiyun to be used for cascading 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- brcm,irq-can-wake: If present, this means the L2 controller can be used as a 20*4882a593Smuzhiyun wakeup source for system suspend/resume. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunhif_intr2_intc: interrupt-controller@f0441000 { 25*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 26*4882a593Smuzhiyun reg = <0xf0441000 0x30>; 27*4882a593Smuzhiyun interrupt-controller; 28*4882a593Smuzhiyun #interrupt-cells = <1>; 29*4882a593Smuzhiyun interrupt-parent = <&intc>; 30*4882a593Smuzhiyun interrupts = <0x0 0x20 0x0>; 31*4882a593Smuzhiyun}; 32