1*4882a593SmuzhiyunBroadcom BCM7038-style Level 1 interrupt controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis block is a first level interrupt controller that is typically connected
4*4882a593Smuzhiyundirectly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
5*4882a593Smuzhiyunsince BCM7038 has contained this hardware.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunKey elements of the hardware design include:
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun- 64, 96, 128, or 160 incoming level IRQ lines
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- Most onchip peripherals are wired directly to an L1 input
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun- A separate instance of the register set for each CPU, allowing individual
14*4882a593Smuzhiyun  peripheral IRQs to be routed to any CPU
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun- Atomic mask/unmask operations
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun- No polarity/level/edge settings
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun- No FIFO or priority encoder logic; software is expected to read all
21*4882a593Smuzhiyun  2-5 status words to determine which IRQs are pending
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunRequired properties:
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun- compatible: should be "brcm,bcm7038-l1-intc"
26*4882a593Smuzhiyun- reg: specifies the base physical address and size of the registers;
27*4882a593Smuzhiyun  the number of supported IRQs is inferred from the size argument
28*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller
29*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an interrupt
30*4882a593Smuzhiyun  source, should be 1.
31*4882a593Smuzhiyun- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
32*4882a593Smuzhiyun  node; valid values depend on the type of parent interrupt controller
33*4882a593Smuzhiyun
34*4882a593SmuzhiyunOptional properties:
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
37*4882a593Smuzhiyun  wakeup source for system suspend/resume.
38*4882a593Smuzhiyun
39*4882a593SmuzhiyunOptional properties:
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
42*4882a593Smuzhiyun  have already been configured by the firmware and should be left unmanaged.
43*4882a593Smuzhiyun  This should have one 32-bit word per status/set/clear/mask group.
44*4882a593Smuzhiyun
45*4882a593SmuzhiyunIf multiple reg ranges and interrupt-parent entries are present on an SMP
46*4882a593Smuzhiyunsystem, the driver will allow IRQ SMP affinity to be set up through the
47*4882a593Smuzhiyun/proc/irq/ interface.  In the simplest possible configuration, only one
48*4882a593Smuzhiyunreg range and one interrupt-parent is needed.
49*4882a593Smuzhiyun
50*4882a593SmuzhiyunExample:
51*4882a593Smuzhiyun
52*4882a593Smuzhiyunperiph_intc: periph_intc@1041a400 {
53*4882a593Smuzhiyun        compatible = "brcm,bcm7038-l1-intc";
54*4882a593Smuzhiyun        reg = <0x1041a400 0x30 0x1041a600 0x30>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun        interrupt-controller;
57*4882a593Smuzhiyun        #interrupt-cells = <1>;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun        interrupt-parent = <&cpu_intc>;
60*4882a593Smuzhiyun        interrupts = <2>, <3>;
61*4882a593Smuzhiyun};
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