1*4882a593SmuzhiyunBroadcom BCM6345-style Level 1 interrupt controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis block is a first level interrupt controller that is typically connected 4*4882a593Smuzhiyundirectly to one of the HW INT lines on each CPU. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunKey elements of the hardware design include: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- 32, 64 or 128 incoming level IRQ lines 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- Most onchip peripherals are wired directly to an L1 input 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- A separate instance of the register set for each CPU, allowing individual 13*4882a593Smuzhiyun peripheral IRQs to be routed to any CPU 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- Contains one or more enable/status word pairs per CPU 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- No atomic set/clear operations 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- No polarity/level/edge settings 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- No FIFO or priority encoder logic; software is expected to read all 22*4882a593Smuzhiyun 2-4 status words to determine which IRQs are pending 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunRequired properties: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" 27*4882a593Smuzhiyun- reg: specifies the base physical address and size of the registers; 28*4882a593Smuzhiyun the number of supported IRQs is inferred from the size argument 29*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 30*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an interrupt 31*4882a593Smuzhiyun source, should be 1. 32*4882a593Smuzhiyun- interrupts: specifies the interrupt line(s) in the interrupt-parent controller 33*4882a593Smuzhiyun node; valid values depend on the type of parent interrupt controller 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunIf multiple reg ranges and interrupt-parent entries are present on an SMP 36*4882a593Smuzhiyunsystem, the driver will allow IRQ SMP affinity to be set up through the 37*4882a593Smuzhiyun/proc/irq/ interface. In the simplest possible configuration, only one 38*4882a593Smuzhiyunreg range and one interrupt-parent is needed. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunThe driver operates in native CPU endian by default, there is no support for 41*4882a593Smuzhiyunspecifying an alternative endianness. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunperiph_intc: interrupt-controller@10000000 { 46*4882a593Smuzhiyun compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; 47*4882a593Smuzhiyun reg = <0x10000020 0x20>, 48*4882a593Smuzhiyun <0x10000040 0x20>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun interrupt-controller; 51*4882a593Smuzhiyun #interrupt-cells = <1>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 54*4882a593Smuzhiyun interrupts = <2>, <3>; 55*4882a593Smuzhiyun}; 56