1*4882a593SmuzhiyunBCM2836 per-CPU interrupt controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe BCM2836 has a per-cpu interrupt controller for the timer, PMU 4*4882a593Smuzhiyunevents, and SMP IPIs. One of the CPUs may receive interrupts for the 5*4882a593Smuzhiyunperipheral (GPU) events, which chain to the BCM2835-style interrupt 6*4882a593Smuzhiyuncontroller. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible: Should be "brcm,bcm2836-l1-intc" 11*4882a593Smuzhiyun- reg: Specifies base physical address and size of the 12*4882a593Smuzhiyun registers 13*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller 14*4882a593Smuzhiyun- #interrupt-cells: Specifies the number of cells needed to encode an 15*4882a593Smuzhiyun interrupt source. The value shall be 2 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common 18*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe interrupt sources are as follows: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun0: CNTPSIRQ 23*4882a593Smuzhiyun1: CNTPNSIRQ 24*4882a593Smuzhiyun2: CNTHPIRQ 25*4882a593Smuzhiyun3: CNTVIRQ 26*4882a593Smuzhiyun8: GPU_FAST 27*4882a593Smuzhiyun9: PMU_FAST 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunlocal_intc: local_intc { 32*4882a593Smuzhiyun compatible = "brcm,bcm2836-l1-intc"; 33*4882a593Smuzhiyun reg = <0x40000000 0x100>; 34*4882a593Smuzhiyun interrupt-controller; 35*4882a593Smuzhiyun #interrupt-cells = <2>; 36*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 37*4882a593Smuzhiyun}; 38