1*4882a593Smuzhiyun* ARM Vectored Interrupt Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunOne or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM 4*4882a593Smuzhiyunsystem for interrupt routing. For multiple controllers they can either be 5*4882a593Smuzhiyunnested or have the outputs wire-OR'd together. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : should be one of 10*4882a593Smuzhiyun "arm,pl190-vic" 11*4882a593Smuzhiyun "arm,pl192-vic" 12*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 13*4882a593Smuzhiyun- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as 14*4882a593Smuzhiyun the VIC has no configuration options for interrupt sources. The cell is a u32 15*4882a593Smuzhiyun and defines the interrupt number. 16*4882a593Smuzhiyun- reg : The register bank for the VIC. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- interrupts : Interrupt source for parent controllers if the VIC is nested. 21*4882a593Smuzhiyun- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit 22*4882a593Smuzhiyun represents single interrupt source, starting from source 0 at LSb and ending 23*4882a593Smuzhiyun at source 31 at MSb. A bit that is set means that the source is wired and 24*4882a593Smuzhiyun clear means otherwise. If unspecified, defaults to all valid. 25*4882a593Smuzhiyun- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be 26*4882a593Smuzhiyun configured as wake up source for the system. Order of bits is the same as for 27*4882a593Smuzhiyun valid-mask property. A set bit means that this interrupt source can be 28*4882a593Smuzhiyun configured as a wake up source for the system. If unspecied, defaults to all 29*4882a593Smuzhiyun interrupt sources configurable as wake up sources. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun vic0: interrupt-controller@60000 { 34*4882a593Smuzhiyun compatible = "arm,pl192-vic"; 35*4882a593Smuzhiyun interrupt-controller; 36*4882a593Smuzhiyun #interrupt-cells = <1>; 37*4882a593Smuzhiyun reg = <0x60000 0x1000>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun valid-mask = <0xffffff7f>; 40*4882a593Smuzhiyun valid-wakeup-mask = <0x0000ff7f>; 41*4882a593Smuzhiyun }; 42