1*4882a593Smuzhiyun* ARM Nested Vector Interrupt Controller (NVIC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe NVIC provides an interrupt controller that is tightly coupled to 4*4882a593SmuzhiyunCortex-M based processor cores. The NVIC implemented on different SoCs 5*4882a593Smuzhiyunvary in the number of interrupts and priority bits per interrupt. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunMain node required properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : should be one of: 10*4882a593Smuzhiyun "arm,v6m-nvic" 11*4882a593Smuzhiyun "arm,v7m-nvic" 12*4882a593Smuzhiyun "arm,v8m-nvic" 13*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 14*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode an 15*4882a593Smuzhiyun interrupt source. The type shall be a <u32> and the value shall be 2. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun The 1st cell contains the interrupt number for the interrupt type. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun The 2nd cell is the priority of the interrupt. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- reg : Specifies base physical address(s) and size of the NVIC registers. 22*4882a593Smuzhiyun This is at a fixed address (0xe000e100) and size (0xc00). 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- arm,num-irq-priority-bits: The number of priority bits implemented by the 25*4882a593Smuzhiyun given SoC 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun intc: interrupt-controller@e000e100 { 30*4882a593Smuzhiyun compatible = "arm,v7m-nvic"; 31*4882a593Smuzhiyun #interrupt-cells = <2>; 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun reg = <0xe000e100 0xc00>; 35*4882a593Smuzhiyun arm,num-irq-priority-bits = <4>; 36*4882a593Smuzhiyun }; 37