1*4882a593Smuzhiyun* ARM Versatile FPGA interrupt controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunOne or more FPGA IRQ controllers can be synthesized in an ARM reference board
4*4882a593Smuzhiyunsuch as the Integrator or Versatile family. The output of these different
5*4882a593Smuzhiyuncontrollers are OR:ed together and fed to the CPU tile's IRQ input. Each
6*4882a593Smuzhiyuninstance can handle up to 32 interrupts.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunRequired properties:
9*4882a593Smuzhiyun- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
10*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller
11*4882a593Smuzhiyun- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
12*4882a593Smuzhiyun  as the FPGA IRQ controller has no configuration options for interrupt
13*4882a593Smuzhiyun  sources.  The cell is a u32 and defines the interrupt number.
14*4882a593Smuzhiyun- reg: The register bank for the FPGA interrupt controller.
15*4882a593Smuzhiyun- clear-mask: a u32 number representing the mask written to clear all IRQs
16*4882a593Smuzhiyun  on the controller at boot for example.
17*4882a593Smuzhiyun- valid-mask: a u32 number representing a bit mask determining which of
18*4882a593Smuzhiyun  the interrupts are valid. Unconnected/unused lines are set to 0, and
19*4882a593Smuzhiyun  the system till not make it possible for devices to request these
20*4882a593Smuzhiyun  interrupts.
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunExample:
23*4882a593Smuzhiyun
24*4882a593Smuzhiyunpic: pic@14000000 {
25*4882a593Smuzhiyun        compatible = "arm,versatile-fpga-irq";
26*4882a593Smuzhiyun        #interrupt-cells = <1>;
27*4882a593Smuzhiyun        interrupt-controller;
28*4882a593Smuzhiyun        reg = <0x14000000 0x100>;
29*4882a593Smuzhiyun        clear-mask = <0xffffffff>;
30*4882a593Smuzhiyun        valid-mask = <0x003fffff>;
31*4882a593Smuzhiyun};
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunOptional properties:
34*4882a593Smuzhiyun- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
35*4882a593Smuzhiyun  output is simply connected to the input of another IRQ controller,
36*4882a593Smuzhiyun  then the parent IRQ shall be specified in this property.
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