1*4882a593SmuzhiyunAlpine MSIX controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSee arm,gic-v3.txt for SPI and MSI definitions. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- compatible: should be "al,alpine-msix" 8*4882a593Smuzhiyun- reg: physical base address and size of the registers 9*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 10*4882a593Smuzhiyun- msi-controller: identifies the node as an PCI Message Signaled Interrupt 11*4882a593Smuzhiyun controller 12*4882a593Smuzhiyun- al,msi-base-spi: SPI base of the MSI frame 13*4882a593Smuzhiyun- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunmsix: msix { 18*4882a593Smuzhiyun compatible = "al,alpine-msix"; 19*4882a593Smuzhiyun reg = <0x0 0xfbe00000 0x0 0x100000>; 20*4882a593Smuzhiyun interrupt-parent = <&gic>; 21*4882a593Smuzhiyun interrupt-controller; 22*4882a593Smuzhiyun msi-controller; 23*4882a593Smuzhiyun al,msi-base-spi = <160>; 24*4882a593Smuzhiyun al,msi-num-spis = <160>; 25*4882a593Smuzhiyun}; 26