1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Actions Semi Owl SoCs SIRQ interrupt controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11*4882a593Smuzhiyun  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
15*4882a593Smuzhiyun  and S900) and provides support for handling up to 3 external interrupt lines.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    enum:
20*4882a593Smuzhiyun      - actions,s500-sirq
21*4882a593Smuzhiyun      - actions,s700-sirq
22*4882a593Smuzhiyun      - actions,s900-sirq
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  reg:
25*4882a593Smuzhiyun    maxItems: 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  interrupt-controller: true
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  '#interrupt-cells':
30*4882a593Smuzhiyun    const: 2
31*4882a593Smuzhiyun    description:
32*4882a593Smuzhiyun      The first cell is the input IRQ number, between 0 and 2, while the second
33*4882a593Smuzhiyun      cell is the trigger type as defined in interrupt.txt in this directory.
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  'interrupts':
36*4882a593Smuzhiyun    description: |
37*4882a593Smuzhiyun      Contains the GIC SPI IRQs mapped to the external interrupt lines.
38*4882a593Smuzhiyun      They shall be specified sequentially from output 0 to 2.
39*4882a593Smuzhiyun    minItems: 3
40*4882a593Smuzhiyun    maxItems: 3
41*4882a593Smuzhiyun
42*4882a593Smuzhiyunrequired:
43*4882a593Smuzhiyun  - compatible
44*4882a593Smuzhiyun  - reg
45*4882a593Smuzhiyun  - interrupt-controller
46*4882a593Smuzhiyun  - '#interrupt-cells'
47*4882a593Smuzhiyun  - 'interrupts'
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunadditionalProperties: false
50*4882a593Smuzhiyun
51*4882a593Smuzhiyunexamples:
52*4882a593Smuzhiyun  - |
53*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun    sirq: interrupt-controller@b01b0200 {
56*4882a593Smuzhiyun      compatible = "actions,s500-sirq";
57*4882a593Smuzhiyun      reg = <0xb01b0200 0x4>;
58*4882a593Smuzhiyun      interrupt-controller;
59*4882a593Smuzhiyun      #interrupt-cells = <2>;
60*4882a593Smuzhiyun      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
61*4882a593Smuzhiyun                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
62*4882a593Smuzhiyun                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
63*4882a593Smuzhiyun    };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun...
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