1*4882a593SmuzhiyunTB10x Top Level Interrupt Controller 2*4882a593Smuzhiyun==================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Abilis TB10x SOC contains a custom interrupt controller. It performs 5*4882a593Smuzhiyunone-to-one mapping of external interrupt sources to CPU interrupts and 6*4882a593Smuzhiyunprovides support for reconfigurable trigger modes. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties 9*4882a593Smuzhiyun------------------- 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- compatible: Should be "abilis,tb10x-ictl" 12*4882a593Smuzhiyun- reg: specifies physical base address and size of register range. 13*4882a593Smuzhiyun- interrupt-congroller: Identifies the node as an interrupt controller. 14*4882a593Smuzhiyun- #interrupt cells: Specifies the number of cells used to encode an interrupt 15*4882a593Smuzhiyun source connected to this controller. The value shall be 2. 16*4882a593Smuzhiyun- interrupts: Specifies the list of interrupt lines which are handled by 17*4882a593Smuzhiyun the interrupt controller in the parent controller's notation. Interrupts 18*4882a593Smuzhiyun are mapped one-to-one to parent interrupts. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample 21*4882a593Smuzhiyun------- 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunintc: interrupt-controller { /* Parent interrupt controller */ 24*4882a593Smuzhiyun interrupt-controller; 25*4882a593Smuzhiyun #interrupt-cells = <1>; /* For example below */ 26*4882a593Smuzhiyun /* ... */ 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyuntb10x_ictl: pic@2000 { /* TB10x interrupt controller */ 30*4882a593Smuzhiyun compatible = "abilis,tb10x-ictl"; 31*4882a593Smuzhiyun reg = <0x2000 0x20>; 32*4882a593Smuzhiyun interrupt-controller; 33*4882a593Smuzhiyun #interrupt-cells = <2>; 34*4882a593Smuzhiyun interrupt-parent = <&intc>; 35*4882a593Smuzhiyun interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36*4882a593Smuzhiyun 20 21 22 23 24 25 26 27 28 29 30 31>; 37*4882a593Smuzhiyun}; 38