1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interconnect/qcom,qcs404.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm QCS404 Network-On-Chip interconnect 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Georgi Djakov <georgi.djakov@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Qualcomm QCS404 interconnect providers support adjusting the 14*4882a593Smuzhiyun bandwidth requirements between the various NoC fabrics. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun enum: 22*4882a593Smuzhiyun - qcom,qcs404-bimc 23*4882a593Smuzhiyun - qcom,qcs404-pcnoc 24*4882a593Smuzhiyun - qcom,qcs404-snoc 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun '#interconnect-cells': 27*4882a593Smuzhiyun const: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clock-names: 30*4882a593Smuzhiyun items: 31*4882a593Smuzhiyun - const: bus 32*4882a593Smuzhiyun - const: bus_a 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clocks: 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun - description: Bus Clock 37*4882a593Smuzhiyun - description: Bus A Clock 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunrequired: 40*4882a593Smuzhiyun - compatible 41*4882a593Smuzhiyun - reg 42*4882a593Smuzhiyun - '#interconnect-cells' 43*4882a593Smuzhiyun - clock-names 44*4882a593Smuzhiyun - clocks 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunadditionalProperties: false 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunexamples: 49*4882a593Smuzhiyun - | 50*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmcc.h> 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun bimc: interconnect@400000 { 53*4882a593Smuzhiyun reg = <0x00400000 0x80000>; 54*4882a593Smuzhiyun compatible = "qcom,qcs404-bimc"; 55*4882a593Smuzhiyun #interconnect-cells = <1>; 56*4882a593Smuzhiyun clock-names = "bus", "bus_a"; 57*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 58*4882a593Smuzhiyun <&rpmcc RPM_SMD_BIMC_A_CLK>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun pnoc: interconnect@500000 { 62*4882a593Smuzhiyun reg = <0x00500000 0x15080>; 63*4882a593Smuzhiyun compatible = "qcom,qcs404-pcnoc"; 64*4882a593Smuzhiyun #interconnect-cells = <1>; 65*4882a593Smuzhiyun clock-names = "bus", "bus_a"; 66*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 67*4882a593Smuzhiyun <&rpmcc RPM_SMD_PNOC_A_CLK>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun snoc: interconnect@580000 { 71*4882a593Smuzhiyun reg = <0x00580000 0x23080>; 72*4882a593Smuzhiyun compatible = "qcom,qcs404-snoc"; 73*4882a593Smuzhiyun #interconnect-cells = <1>; 74*4882a593Smuzhiyun clock-names = "bus", "bus_a"; 75*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 76*4882a593Smuzhiyun <&rpmcc RPM_SMD_SNOC_A_CLK>; 77*4882a593Smuzhiyun }; 78