1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 DAC bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC 11*4882a593Smuzhiyun may be configured in 8 or 12-bit mode. It has two output channels, each with 12*4882a593Smuzhiyun its own converter. 13*4882a593Smuzhiyun It has built-in noise and triangle waveform generator and supports external 14*4882a593Smuzhiyun triggers for conversions. The DAC's output buffer allows a high drive output 15*4882a593Smuzhiyun current. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunmaintainers: 18*4882a593Smuzhiyun - Fabrice Gasnier <fabrice.gasnier@st.com> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun enum: 23*4882a593Smuzhiyun - st,stm32f4-dac-core 24*4882a593Smuzhiyun - st,stm32h7-dac-core 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun resets: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clocks: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock-names: 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - const: pclk 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun vref-supply: 40*4882a593Smuzhiyun description: Phandle to the vref input analog reference voltage. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#address-cells': 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun '#size-cells': 46*4882a593Smuzhiyun const: 0 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrequired: 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun - reg 53*4882a593Smuzhiyun - clocks 54*4882a593Smuzhiyun - clock-names 55*4882a593Smuzhiyun - vref-supply 56*4882a593Smuzhiyun - '#address-cells' 57*4882a593Smuzhiyun - '#size-cells' 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunpatternProperties: 60*4882a593Smuzhiyun "^dac@[1-2]+$": 61*4882a593Smuzhiyun type: object 62*4882a593Smuzhiyun description: 63*4882a593Smuzhiyun A DAC block node should contain at least one subnode, representing an 64*4882a593Smuzhiyun DAC instance/channel available on the machine. 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun properties: 67*4882a593Smuzhiyun compatible: 68*4882a593Smuzhiyun const: st,stm32-dac 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun reg: 71*4882a593Smuzhiyun description: Must be either 1 or 2, to define (single) channel in use 72*4882a593Smuzhiyun enum: [1, 2] 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun '#io-channel-cells': 75*4882a593Smuzhiyun const: 1 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun additionalProperties: false 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun required: 80*4882a593Smuzhiyun - compatible 81*4882a593Smuzhiyun - reg 82*4882a593Smuzhiyun - '#io-channel-cells' 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunexamples: 85*4882a593Smuzhiyun - | 86*4882a593Smuzhiyun // Example on stm32mp157c 87*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 88*4882a593Smuzhiyun dac: dac@40017000 { 89*4882a593Smuzhiyun compatible = "st,stm32h7-dac-core"; 90*4882a593Smuzhiyun reg = <0x40017000 0x400>; 91*4882a593Smuzhiyun clocks = <&rcc DAC12>; 92*4882a593Smuzhiyun clock-names = "pclk"; 93*4882a593Smuzhiyun vref-supply = <&vref>; 94*4882a593Smuzhiyun #address-cells = <1>; 95*4882a593Smuzhiyun #size-cells = <0>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun dac@1 { 98*4882a593Smuzhiyun compatible = "st,stm32-dac"; 99*4882a593Smuzhiyun #io-channel-cells = <1>; 100*4882a593Smuzhiyun reg = <1>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun dac@2 { 104*4882a593Smuzhiyun compatible = "st,stm32-dac"; 105*4882a593Smuzhiyun #io-channel-cells = <1>; 106*4882a593Smuzhiyun reg = <2>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun... 111