1*4882a593Smuzhiyun* Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Has to contain one of the following: 5*4882a593Smuzhiyun adi,ad5755 6*4882a593Smuzhiyun adi,ad5755-1 7*4882a593Smuzhiyun adi,ad5757 8*4882a593Smuzhiyun adi,ad5735 9*4882a593Smuzhiyun adi,ad5737 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg: spi chip select number for the device 12*4882a593Smuzhiyun - spi-cpha or spi-cpol: is the only modes that is supported 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRecommended properties: 15*4882a593Smuzhiyun - spi-max-frequency: Definition as per 16*4882a593Smuzhiyun Documentation/devicetree/bindings/spi/spi-bus.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593SmuzhiyunSee include/dt-bindings/iio/ad5755.h 20*4882a593Smuzhiyun - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an 21*4882a593Smuzhiyun external resistor and thereby bypasses 22*4882a593Smuzhiyun the internal compensation resistor. 23*4882a593Smuzhiyun - adi,dc-dc-phase: 24*4882a593Smuzhiyun Valid values for DC DC Phase control is: 25*4882a593Smuzhiyun 0: All dc-to-dc converters clock on the same edge. 26*4882a593Smuzhiyun 1: Channel A and Channel B clock on the same edge, 27*4882a593Smuzhiyun Channel C and Channel D clock on opposite edges. 28*4882a593Smuzhiyun 2: Channel A and Channel C clock on the same edge, 29*4882a593Smuzhiyun Channel B and Channel D clock on opposite edges. 30*4882a593Smuzhiyun 3: Channel A, Channel B, Channel C, and Channel D 31*4882a593Smuzhiyun clock 90 degrees out of phase from each other. 32*4882a593Smuzhiyun - adi,dc-dc-freq-hz: 33*4882a593Smuzhiyun Valid values for DC DC frequency is [Hz]: 34*4882a593Smuzhiyun 250000 35*4882a593Smuzhiyun 410000 36*4882a593Smuzhiyun 650000 37*4882a593Smuzhiyun - adi,dc-dc-max-microvolt: 38*4882a593Smuzhiyun Valid values for the maximum allowed Vboost voltage supplied by 39*4882a593Smuzhiyun the dc-to-dc converter is: 40*4882a593Smuzhiyun 23000000 41*4882a593Smuzhiyun 24500000 42*4882a593Smuzhiyun 27000000 43*4882a593Smuzhiyun 29500000 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunOptional for every channel: 46*4882a593Smuzhiyun - adi,mode: 47*4882a593Smuzhiyun Valid values for DAC modes is: 48*4882a593Smuzhiyun 0: 0 V to 5 V voltage range. 49*4882a593Smuzhiyun 1: 0 V to 10 V voltage range. 50*4882a593Smuzhiyun 2: Plus minus 5 V voltage range. 51*4882a593Smuzhiyun 3: Plus minus 10 V voltage range. 52*4882a593Smuzhiyun 4: 4 mA to 20 mA current range. 53*4882a593Smuzhiyun 5: 0 mA to 20 mA current range. 54*4882a593Smuzhiyun 6: 0 mA to 24 mA current range. 55*4882a593Smuzhiyun - adi,ext-current-sense-resistor: boolean set if the hardware a external 56*4882a593Smuzhiyun current sense resistor. 57*4882a593Smuzhiyun - adi,enable-voltage-overrange: boolean enable voltage overrange 58*4882a593Smuzhiyun - adi,slew: Array of slewrate settings should contain 3 fields: 59*4882a593Smuzhiyun 1: Should be either 0 or 1 in order to enable or disable slewrate. 60*4882a593Smuzhiyun 2: Slew rate settings: 61*4882a593Smuzhiyun Valid values for the slew rate update frequency: 62*4882a593Smuzhiyun 64000 63*4882a593Smuzhiyun 32000 64*4882a593Smuzhiyun 16000 65*4882a593Smuzhiyun 8000 66*4882a593Smuzhiyun 4000 67*4882a593Smuzhiyun 2000 68*4882a593Smuzhiyun 1000 69*4882a593Smuzhiyun 500 70*4882a593Smuzhiyun 250 71*4882a593Smuzhiyun 125 72*4882a593Smuzhiyun 64 73*4882a593Smuzhiyun 32 74*4882a593Smuzhiyun 16 75*4882a593Smuzhiyun 8 76*4882a593Smuzhiyun 4 77*4882a593Smuzhiyun 0 78*4882a593Smuzhiyun 3: Slew step size: 79*4882a593Smuzhiyun Valid values for the step size LSBs: 80*4882a593Smuzhiyun 1 81*4882a593Smuzhiyun 2 82*4882a593Smuzhiyun 4 83*4882a593Smuzhiyun 16 84*4882a593Smuzhiyun 32 85*4882a593Smuzhiyun 64 86*4882a593Smuzhiyun 128 87*4882a593Smuzhiyun 256 88*4882a593Smuzhiyun 89*4882a593SmuzhiyunExample: 90*4882a593Smuzhiyundac@0 { 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <0>; 93*4882a593Smuzhiyun compatible = "adi,ad5755"; 94*4882a593Smuzhiyun reg = <0>; 95*4882a593Smuzhiyun spi-max-frequency = <1000000>; 96*4882a593Smuzhiyun spi-cpha; 97*4882a593Smuzhiyun adi,dc-dc-phase = <0>; 98*4882a593Smuzhiyun adi,dc-dc-freq-hz = <410000>; 99*4882a593Smuzhiyun adi,dc-dc-max-microvolt = <23000000>; 100*4882a593Smuzhiyun channel@0 { 101*4882a593Smuzhiyun reg = <0>; 102*4882a593Smuzhiyun adi,mode = <4>; 103*4882a593Smuzhiyun adi,ext-current-sense-resistor; 104*4882a593Smuzhiyun adi,slew = <0 64000 1>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun channel@1 { 107*4882a593Smuzhiyun reg = <1>; 108*4882a593Smuzhiyun adi,mode = <4>; 109*4882a593Smuzhiyun adi,ext-current-sense-resistor; 110*4882a593Smuzhiyun adi,slew = <0 64000 1>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun channel@2 { 113*4882a593Smuzhiyun reg = <2>; 114*4882a593Smuzhiyun adi,mode = <4>; 115*4882a593Smuzhiyun adi,ext-current-sense-resistor; 116*4882a593Smuzhiyun adi,slew = <0 64000 1>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun channel@3 { 119*4882a593Smuzhiyun reg = <3>; 120*4882a593Smuzhiyun adi,mode = <4>; 121*4882a593Smuzhiyun adi,ext-current-sense-resistor; 122*4882a593Smuzhiyun adi,slew = <0 64000 1>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125