1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/ti,adc12138.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Texas Instruments ADC12138 and similar self-calibrating ADCs 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Akinobu Mita <akinobu.mita@gmail.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun 13 bit ADCs with 1, 2 or 8 inputs and self calibrating circuitry to 14*4882a593Smuzhiyun correct for linearity, zero and full scale errors. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - ti,adc12130 20*4882a593Smuzhiyun - ti,adc12132 21*4882a593Smuzhiyun - ti,adc12138 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun description: End of Conversion (EOC) interrupt 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun description: Conversion clock input. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun spi-max-frequency: true 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun vref-p-supply: 37*4882a593Smuzhiyun description: The regulator supply for positive analog voltage reference 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun vref-n-supply: 40*4882a593Smuzhiyun description: | 41*4882a593Smuzhiyun The regulator supply for negative analog voltage reference 42*4882a593Smuzhiyun (Note that this must not go below GND or exceed vref-p) 43*4882a593Smuzhiyun If not specified, this is assumed to be analog ground. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun ti,acquisition-time: 46*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 47*4882a593Smuzhiyun enum: [ 6, 10, 18, 34 ] 48*4882a593Smuzhiyun description: | 49*4882a593Smuzhiyun The number of conversion clock periods for the S/H's acquisition time. 50*4882a593Smuzhiyun For high source impedances, this value can be increased to 18 or 34. 51*4882a593Smuzhiyun For less ADC accuracy and/or slower CCLK frequencies this value may be 52*4882a593Smuzhiyun decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the 53*4882a593Smuzhiyun datasheet for details. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun "#io-channel-cells": 56*4882a593Smuzhiyun const: 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunrequired: 59*4882a593Smuzhiyun - compatible 60*4882a593Smuzhiyun - reg 61*4882a593Smuzhiyun - interrupts 62*4882a593Smuzhiyun - clocks 63*4882a593Smuzhiyun - vref-p-supply 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun - | 69*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 70*4882a593Smuzhiyun spi { 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun adc@0 { 75*4882a593Smuzhiyun compatible = "ti,adc12138"; 76*4882a593Smuzhiyun reg = <0>; 77*4882a593Smuzhiyun interrupts = <28 IRQ_TYPE_EDGE_RISING>; 78*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 79*4882a593Smuzhiyun clocks = <&cclk>; 80*4882a593Smuzhiyun vref-p-supply = <&ldo4_reg>; 81*4882a593Smuzhiyun spi-max-frequency = <5000000>; 82*4882a593Smuzhiyun ti,acquisition-time = <6>; 83*4882a593Smuzhiyun #io-channel-cells = <1>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun... 87