1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/rockchip-saradc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Rockchip Successive Approximation Register (SAR) A/D Converter 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Heiko Stuebner <heiko@sntech.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun oneOf: 15*4882a593Smuzhiyun - const: rockchip,saradc 16*4882a593Smuzhiyun - const: rockchip,rk3066-tsadc 17*4882a593Smuzhiyun - const: rockchip,rk3399-saradc 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - enum: 20*4882a593Smuzhiyun - rockchip,px30-saradc 21*4882a593Smuzhiyun - rockchip,rk1808-saradc 22*4882a593Smuzhiyun - rockchip,rk3308-saradc 23*4882a593Smuzhiyun - rockchip,rk3328-saradc 24*4882a593Smuzhiyun - rockchip,rv1108-saradc 25*4882a593Smuzhiyun - const: rockchip,rk3399-saradc 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - description: converter clock 36*4882a593Smuzhiyun - description: peripheral clock 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clock-names: 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - const: saradc 41*4882a593Smuzhiyun - const: apb_pclk 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun resets: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun reset-names: 47*4882a593Smuzhiyun const: saradc-apb 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun vref-supply: 50*4882a593Smuzhiyun description: 51*4882a593Smuzhiyun The regulator supply for the ADC reference voltage. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun "#io-channel-cells": 54*4882a593Smuzhiyun const: 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunrequired: 57*4882a593Smuzhiyun - compatible 58*4882a593Smuzhiyun - reg 59*4882a593Smuzhiyun - interrupts 60*4882a593Smuzhiyun - clocks 61*4882a593Smuzhiyun - clock-names 62*4882a593Smuzhiyun - vref-supply 63*4882a593Smuzhiyun - "#io-channel-cells" 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun - | 69*4882a593Smuzhiyun #include <dt-bindings/clock/rk3288-cru.h> 70*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 71*4882a593Smuzhiyun saradc: saradc@2006c000 { 72*4882a593Smuzhiyun compatible = "rockchip,saradc"; 73*4882a593Smuzhiyun reg = <0x2006c000 0x100>; 74*4882a593Smuzhiyun interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 75*4882a593Smuzhiyun clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 76*4882a593Smuzhiyun clock-names = "saradc", "apb_pclk"; 77*4882a593Smuzhiyun resets = <&cru SRST_SARADC>; 78*4882a593Smuzhiyun reset-names = "saradc-apb"; 79*4882a593Smuzhiyun vref-supply = <&vcc18>; 80*4882a593Smuzhiyun #io-channel-cells = <1>; 81*4882a593Smuzhiyun }; 82