1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/nxp,lpc3220-adc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP LPC3220 SoC ADC controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Gregory Clement <gregory.clement@bootlin.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun This hardware block has been used on several LPC32XX SoCs. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: nxp,lpc3220-adc 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun vref-supply: true 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun "#io-channel-cells": 28*4882a593Smuzhiyun const: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - compatible 32*4882a593Smuzhiyun - reg 33*4882a593Smuzhiyun - interrupts 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunadditionalProperties: false 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunexamples: 38*4882a593Smuzhiyun - | 39*4882a593Smuzhiyun soc { 40*4882a593Smuzhiyun #address-cells = <1>; 41*4882a593Smuzhiyun #size-cells = <1>; 42*4882a593Smuzhiyun adc@40048000 { 43*4882a593Smuzhiyun compatible = "nxp,lpc3220-adc"; 44*4882a593Smuzhiyun reg = <0x40048000 0x1000>; 45*4882a593Smuzhiyun interrupt-parent = <&mic>; 46*4882a593Smuzhiyun interrupts = <39 0>; 47*4882a593Smuzhiyun vref-supply = <&vcc>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun... 51