1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/nxp,lpc1850-adc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP LPC1850 ADC bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Joachim Eastwood <manabian@gmail.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun Supports the ADC found on the LPC1850 SoC. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: nxp,lpc1850-adc 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vref-supply: true 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun resets: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun "#io-channel-cells": 34*4882a593Smuzhiyun const: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunrequired: 37*4882a593Smuzhiyun - compatible 38*4882a593Smuzhiyun - reg 39*4882a593Smuzhiyun - interrupts 40*4882a593Smuzhiyun - clocks 41*4882a593Smuzhiyun - vref-supply 42*4882a593Smuzhiyun - resets 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunadditionalProperties: false 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunexamples: 47*4882a593Smuzhiyun - | 48*4882a593Smuzhiyun #include <dt-bindings/clock/lpc18xx-ccu.h> 49*4882a593Smuzhiyun soc { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <1>; 52*4882a593Smuzhiyun adc@400e3000 { 53*4882a593Smuzhiyun compatible = "nxp,lpc1850-adc"; 54*4882a593Smuzhiyun reg = <0x400e3000 0x1000>; 55*4882a593Smuzhiyun interrupts = <17>; 56*4882a593Smuzhiyun clocks = <&ccu1 CLK_APB3_ADC0>; 57*4882a593Smuzhiyun vref-supply = <®_vdda>; 58*4882a593Smuzhiyun resets = <&rgu 40>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun... 62