1*4882a593Smuzhiyun* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc (mt65xx/mt81xx/mt27xx) 2*4882a593Smuzhiyun=============== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Auxiliary Analog/Digital Converter (AUXADC) is an ADC found 5*4882a593Smuzhiyunin some Mediatek SoCs which among other things measures the temperatures 6*4882a593Smuzhiyunin the SoC. It can be used directly with register accesses, but it is also 7*4882a593Smuzhiyunused by thermal controller which reads the temperatures from the AUXADC 8*4882a593Smuzhiyundirectly via its own bus interface. See 9*4882a593SmuzhiyunDocumentation/devicetree/bindings/thermal/mediatek-thermal.txt 10*4882a593Smuzhiyunfor the Thermal Controller which holds a phandle to the AUXADC. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun - compatible: Should be one of: 14*4882a593Smuzhiyun - "mediatek,mt2701-auxadc": For MT2701 family of SoCs 15*4882a593Smuzhiyun - "mediatek,mt2712-auxadc": For MT2712 family of SoCs 16*4882a593Smuzhiyun - "mediatek,mt6765-auxadc": For MT6765 family of SoCs 17*4882a593Smuzhiyun - "mediatek,mt7622-auxadc": For MT7622 family of SoCs 18*4882a593Smuzhiyun - "mediatek,mt8173-auxadc": For MT8173 family of SoCs 19*4882a593Smuzhiyun - "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs 20*4882a593Smuzhiyun - reg: Address range of the AUXADC unit. 21*4882a593Smuzhiyun - clocks: Should contain a clock specifier for each entry in clock-names 22*4882a593Smuzhiyun - clock-names: Should contain "main". 23*4882a593Smuzhiyun - #io-channel-cells: Should be 1, see ../iio-bindings.txt 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunauxadc: adc@11001000 { 28*4882a593Smuzhiyun compatible = "mediatek,mt2701-auxadc"; 29*4882a593Smuzhiyun reg = <0 0x11001000 0 0x1000>; 30*4882a593Smuzhiyun clocks = <&pericfg CLK_PERI_AUXADC>; 31*4882a593Smuzhiyun clock-names = "main"; 32*4882a593Smuzhiyun #io-channel-cells = <1>; 33*4882a593Smuzhiyun}; 34