1*4882a593Smuzhiyun* AT91 SAMA5D2 Analog to Digital Converter (ADC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc". 5*4882a593Smuzhiyun - reg: Should contain ADC registers location and length. 6*4882a593Smuzhiyun - interrupts: Should contain the IRQ line for the ADC. 7*4882a593Smuzhiyun - clocks: phandle to device clock. 8*4882a593Smuzhiyun - clock-names: Must be "adc_clk". 9*4882a593Smuzhiyun - vref-supply: Supply used as reference for conversions. 10*4882a593Smuzhiyun - vddana-supply: Supply for the adc device. 11*4882a593Smuzhiyun - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC. 12*4882a593Smuzhiyun - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC. 13*4882a593Smuzhiyun - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC. 14*4882a593Smuzhiyun - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware 15*4882a593Smuzhiyun trigger pin. When the specific edge type is detected, the conversion will 16*4882a593Smuzhiyun start. Possible values are rising, falling, or both. 17*4882a593Smuzhiyun This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING , 18*4882a593Smuzhiyun IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun - dmas: Phandle to dma channel for the ADC. 22*4882a593Smuzhiyun - dma-names: Must be "rx" when dmas property is being used. 23*4882a593Smuzhiyun See ../../dma/dma.txt for details. 24*4882a593Smuzhiyun - #io-channel-cells: in case consumer drivers are attached, this must be 1. 25*4882a593Smuzhiyun See <Documentation/devicetree/bindings/iio/iio-bindings.txt> for details. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunProperties for consumer drivers: 28*4882a593Smuzhiyun - Consumer drivers can be connected to this producer device, as specified 29*4882a593Smuzhiyun in <Documentation/devicetree/bindings/iio/iio-bindings.txt> 30*4882a593Smuzhiyun - Channels exposed are specified in: 31*4882a593Smuzhiyun <dt-bindings/iio/adc/at91-sama5d2_adc.txt> 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunadc: adc@fc030000 { 36*4882a593Smuzhiyun compatible = "atmel,sama5d2-adc"; 37*4882a593Smuzhiyun reg = <0xfc030000 0x100>; 38*4882a593Smuzhiyun interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 39*4882a593Smuzhiyun clocks = <&adc_clk>; 40*4882a593Smuzhiyun clock-names = "adc_clk"; 41*4882a593Smuzhiyun atmel,min-sample-rate-hz = <200000>; 42*4882a593Smuzhiyun atmel,max-sample-rate-hz = <20000000>; 43*4882a593Smuzhiyun atmel,startup-time-ms = <4>; 44*4882a593Smuzhiyun vddana-supply = <&vdd_3v3_lp_reg>; 45*4882a593Smuzhiyun vref-supply = <&vdd_3v3_lp_reg>; 46*4882a593Smuzhiyun atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>; 47*4882a593Smuzhiyun dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 48*4882a593Smuzhiyun dma-names = "rx"; 49*4882a593Smuzhiyun #io-channel-cells = <1>; 50*4882a593Smuzhiyun} 51