1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Analog Devices AD7768-1 ADC device driver 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Michael Hennerich <michael.hennerich@analog.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Datasheet at: 14*4882a593Smuzhiyun https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: adi,ad7768-1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clocks: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clock-names: 27*4882a593Smuzhiyun const: mclk 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun interrupts: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun vref-supply: 33*4882a593Smuzhiyun description: 34*4882a593Smuzhiyun ADC reference voltage supply 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun adi,sync-in-gpios: 37*4882a593Smuzhiyun description: 38*4882a593Smuzhiyun Enables synchronization of multiple devices that require simultaneous 39*4882a593Smuzhiyun sampling. A pulse is always required if the configuration is changed 40*4882a593Smuzhiyun in any way, for example if the filter decimation rate changes. 41*4882a593Smuzhiyun As the line is active low, it should be marked GPIO_ACTIVE_LOW. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun reset-gpios: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun spi-max-frequency: true 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun spi-cpol: true 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun spi-cpha: true 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun "#io-channel-cells": 53*4882a593Smuzhiyun const: 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunrequired: 56*4882a593Smuzhiyun - compatible 57*4882a593Smuzhiyun - reg 58*4882a593Smuzhiyun - clocks 59*4882a593Smuzhiyun - clock-names 60*4882a593Smuzhiyun - vref-supply 61*4882a593Smuzhiyun - spi-cpol 62*4882a593Smuzhiyun - spi-cpha 63*4882a593Smuzhiyun - adi,sync-in-gpios 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun - | 69*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 70*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 71*4882a593Smuzhiyun spi { 72*4882a593Smuzhiyun #address-cells = <1>; 73*4882a593Smuzhiyun #size-cells = <0>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun adc@0 { 76*4882a593Smuzhiyun compatible = "adi,ad7768-1"; 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun spi-max-frequency = <2000000>; 79*4882a593Smuzhiyun spi-cpol; 80*4882a593Smuzhiyun spi-cpha; 81*4882a593Smuzhiyun vref-supply = <&adc_vref>; 82*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_EDGE_RISING>; 83*4882a593Smuzhiyun interrupt-parent = <&gpio>; 84*4882a593Smuzhiyun adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; 85*4882a593Smuzhiyun reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>; 86*4882a593Smuzhiyun clocks = <&ad7768_mclk>; 87*4882a593Smuzhiyun clock-names = "mclk"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun... 91