1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2019 Analog Devices Inc. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iio/adc/adi,ad7124.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Analog Devices AD7124 ADC device driver 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Stefan Popa <stefan.popa@analog.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Bindings for the Analog Devices AD7124 ADC device. Datasheet can be 15*4882a593Smuzhiyun found here: 16*4882a593Smuzhiyun https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - adi,ad7124-4 22*4882a593Smuzhiyun - adi,ad7124-8 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun description: SPI chip select number for the device 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun description: phandle to the master clock (mclk) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: mclk 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupts: 37*4882a593Smuzhiyun description: IRQ line for the ADC 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun '#address-cells': 41*4882a593Smuzhiyun const: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun '#size-cells': 44*4882a593Smuzhiyun const: 0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun refin1-supply: 47*4882a593Smuzhiyun description: refin1 supply can be used as reference for conversion. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun refin2-supply: 50*4882a593Smuzhiyun description: refin2 supply can be used as reference for conversion. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun avdd-supply: 53*4882a593Smuzhiyun description: avdd supply can be used as reference for conversion. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun spi-max-frequency: true 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunrequired: 58*4882a593Smuzhiyun - compatible 59*4882a593Smuzhiyun - reg 60*4882a593Smuzhiyun - clocks 61*4882a593Smuzhiyun - clock-names 62*4882a593Smuzhiyun - interrupts 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunpatternProperties: 65*4882a593Smuzhiyun "^channel@([0-9]|1[0-5])$": 66*4882a593Smuzhiyun type: object 67*4882a593Smuzhiyun description: | 68*4882a593Smuzhiyun Represents the external channels which are connected to the ADC. 69*4882a593Smuzhiyun See Documentation/devicetree/bindings/iio/adc/adc.txt. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun properties: 72*4882a593Smuzhiyun reg: 73*4882a593Smuzhiyun description: | 74*4882a593Smuzhiyun The channel number. It can have up to 8 channels on ad7124-4 75*4882a593Smuzhiyun and 16 channels on ad7124-8, numbered from 0 to 15. 76*4882a593Smuzhiyun items: 77*4882a593Smuzhiyun minimum: 0 78*4882a593Smuzhiyun maximum: 15 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun adi,reference-select: 81*4882a593Smuzhiyun description: | 82*4882a593Smuzhiyun Select the reference source to use when converting on 83*4882a593Smuzhiyun the specific channel. Valid values are: 84*4882a593Smuzhiyun 0: REFIN1(+)/REFIN1(−). 85*4882a593Smuzhiyun 1: REFIN2(+)/REFIN2(−). 86*4882a593Smuzhiyun 3: AVDD 87*4882a593Smuzhiyun If this field is left empty, internal reference is selected. 88*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 89*4882a593Smuzhiyun enum: [0, 1, 3] 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun diff-channels: 92*4882a593Smuzhiyun description: see Documentation/devicetree/bindings/iio/adc/adc.txt 93*4882a593Smuzhiyun items: 94*4882a593Smuzhiyun minimum: 0 95*4882a593Smuzhiyun maximum: 15 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun bipolar: 98*4882a593Smuzhiyun description: see Documentation/devicetree/bindings/iio/adc/adc.txt 99*4882a593Smuzhiyun type: boolean 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun adi,buffered-positive: 102*4882a593Smuzhiyun description: Enable buffered mode for positive input. 103*4882a593Smuzhiyun type: boolean 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun adi,buffered-negative: 106*4882a593Smuzhiyun description: Enable buffered mode for negative input. 107*4882a593Smuzhiyun type: boolean 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun required: 110*4882a593Smuzhiyun - reg 111*4882a593Smuzhiyun - diff-channels 112*4882a593Smuzhiyun 113*4882a593SmuzhiyunadditionalProperties: false 114*4882a593Smuzhiyun 115*4882a593Smuzhiyunexamples: 116*4882a593Smuzhiyun - | 117*4882a593Smuzhiyun spi { 118*4882a593Smuzhiyun #address-cells = <1>; 119*4882a593Smuzhiyun #size-cells = <0>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun adc@0 { 122*4882a593Smuzhiyun compatible = "adi,ad7124-4"; 123*4882a593Smuzhiyun reg = <0>; 124*4882a593Smuzhiyun spi-max-frequency = <5000000>; 125*4882a593Smuzhiyun interrupts = <25 2>; 126*4882a593Smuzhiyun interrupt-parent = <&gpio>; 127*4882a593Smuzhiyun refin1-supply = <&adc_vref>; 128*4882a593Smuzhiyun clocks = <&ad7124_mclk>; 129*4882a593Smuzhiyun clock-names = "mclk"; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #address-cells = <1>; 132*4882a593Smuzhiyun #size-cells = <0>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun channel@0 { 135*4882a593Smuzhiyun reg = <0>; 136*4882a593Smuzhiyun diff-channels = <0 1>; 137*4882a593Smuzhiyun adi,reference-select = <0>; 138*4882a593Smuzhiyun adi,buffered-positive; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun channel@1 { 142*4882a593Smuzhiyun reg = <1>; 143*4882a593Smuzhiyun bipolar; 144*4882a593Smuzhiyun diff-channels = <2 3>; 145*4882a593Smuzhiyun adi,reference-select = <0>; 146*4882a593Smuzhiyun adi,buffered-positive; 147*4882a593Smuzhiyun adi,buffered-negative; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun channel@2 { 151*4882a593Smuzhiyun reg = <2>; 152*4882a593Smuzhiyun diff-channels = <4 5>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun channel@3 { 156*4882a593Smuzhiyun reg = <3>; 157*4882a593Smuzhiyun diff-channels = <6 7>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161