1*4882a593SmuzhiyunBindings for Synopsys DesignWare I3C master block 2*4882a593Smuzhiyun================================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun-------------------- 6*4882a593Smuzhiyun- compatible: shall be "snps,dw-i3c-master-1.00a" 7*4882a593Smuzhiyun- clocks: shall reference the core_clk 8*4882a593Smuzhiyun- interrupts: the interrupt line connected to this I3C master 9*4882a593Smuzhiyun- reg: Offset and length of I3C master registers 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunMandatory properties defined by the generic binding (see 12*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details): 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- #address-cells: shall be set to 3 15*4882a593Smuzhiyun- #size-cells: shall be set to 0 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties defined by the generic binding (see 18*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details): 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- i2c-scl-hz 21*4882a593Smuzhiyun- i3c-scl-hz 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunI3C device connected on the bus follow the generic description (see 24*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details). 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun i3c-master@2000 { 29*4882a593Smuzhiyun compatible = "snps,dw-i3c-master-1.00a"; 30*4882a593Smuzhiyun #address-cells = <3>; 31*4882a593Smuzhiyun #size-cells = <0>; 32*4882a593Smuzhiyun reg = <0x02000 0x1000>; 33*4882a593Smuzhiyun interrupts = <0>; 34*4882a593Smuzhiyun clocks = <&i3cclk>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun eeprom@57{ 37*4882a593Smuzhiyun compatible = "atmel,24c01"; 38*4882a593Smuzhiyun reg = <0x57 0x0 0x10>; 39*4882a593Smuzhiyun pagesize = <0x8>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42