1*4882a593SmuzhiyunBindings for cadence I3C master block 2*4882a593Smuzhiyun===================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun-------------------- 6*4882a593Smuzhiyun- compatible: shall be "cdns,i3c-master" 7*4882a593Smuzhiyun- clocks: shall reference the pclk and sysclk 8*4882a593Smuzhiyun- clock-names: shall contain "pclk" and "sysclk" 9*4882a593Smuzhiyun- interrupts: the interrupt line connected to this I3C master 10*4882a593Smuzhiyun- reg: I3C master registers 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunMandatory properties defined by the generic binding (see 13*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details): 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #address-cells: shall be set to 1 16*4882a593Smuzhiyun- #size-cells: shall be set to 0 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties defined by the generic binding (see 19*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details): 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- i2c-scl-hz 22*4882a593Smuzhiyun- i3c-scl-hz 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunI3C device connected on the bus follow the generic description (see 25*4882a593SmuzhiyunDocumentation/devicetree/bindings/i3c/i3c.txt for more details). 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun i3c-master@0d040000 { 30*4882a593Smuzhiyun compatible = "cdns,i3c-master"; 31*4882a593Smuzhiyun clocks = <&coreclock>, <&i3csysclock>; 32*4882a593Smuzhiyun clock-names = "pclk", "sysclk"; 33*4882a593Smuzhiyun interrupts = <3 0>; 34*4882a593Smuzhiyun reg = <0x0d040000 0x1000>; 35*4882a593Smuzhiyun #address-cells = <1>; 36*4882a593Smuzhiyun #size-cells = <0>; 37*4882a593Smuzhiyun i2c-scl-hz = <100000>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun nunchuk: nunchuk@52 { 40*4882a593Smuzhiyun compatible = "nintendo,nunchuk"; 41*4882a593Smuzhiyun reg = <0x52 0x0 0x10>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44