1*4882a593SmuzhiyunQualcomm Universal Peripheral (QUP) I2C controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Should be: 5*4882a593Smuzhiyun * "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064. 6*4882a593Smuzhiyun * "qcom,i2c-qup-v2.1.1" for 8974 v1. 7*4882a593Smuzhiyun * "qcom,i2c-qup-v2.2.1" for 8974 v2 and later. 8*4882a593Smuzhiyun - reg: Should contain QUP register address and length. 9*4882a593Smuzhiyun - interrupts: Should contain I2C interrupt. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - clocks: A list of phandles + clock-specifiers, one for each entry in 12*4882a593Smuzhiyun clock-names. 13*4882a593Smuzhiyun - clock-names: Should contain: 14*4882a593Smuzhiyun * "core" for the core clock 15*4882a593Smuzhiyun * "iface" for the AHB clock 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun - #address-cells: Should be <1> Address cells for i2c device address 18*4882a593Smuzhiyun - #size-cells: Should be <0> as i2c addresses have no size component 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun - clock-frequency: Should specify the desired i2c bus clock frequency in Hz, 22*4882a593Smuzhiyun defaults to 100kHz if omitted. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunChild nodes should conform to i2c bus binding. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun i2c@f9924000 { 29*4882a593Smuzhiyun compatible = "qcom,i2c-qup-v2.2.1"; 30*4882a593Smuzhiyun reg = <0xf9924000 0x1000>; 31*4882a593Smuzhiyun interrupts = <0 96 0>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 34*4882a593Smuzhiyun clock-names = "core", "iface"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-frequency = <355000>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <0>; 40*4882a593Smuzhiyun }; 41