1*4882a593SmuzhiyunNVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or 5*4882a593Smuzhiyun "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". 6*4882a593Smuzhiyun For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be 7*4882a593Smuzhiyun "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is 8*4882a593Smuzhiyun tegra124, tegra132, or tegra210. 9*4882a593Smuzhiyun Details of compatible are as follows: 10*4882a593Smuzhiyun nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C 11*4882a593Smuzhiyun controller. This only support master mode of I2C communication. Register 12*4882a593Smuzhiyun interface/offset and interrupts handling are different than generic I2C 13*4882a593Smuzhiyun controller. Driver of DVC I2C controller is only compatible with 14*4882a593Smuzhiyun "nvidia,tegra20-i2c-dvc". 15*4882a593Smuzhiyun nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support 16*4882a593Smuzhiyun master and slave mode of I2C communication. The i2c-tegra driver only 17*4882a593Smuzhiyun support master mode of I2C communication. Driver of I2C controller is 18*4882a593Smuzhiyun only compatible with "nvidia,tegra20-i2c". 19*4882a593Smuzhiyun nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is 20*4882a593Smuzhiyun very much similar to Tegra20 I2C controller with additional feature: 21*4882a593Smuzhiyun Continue Transfer Support. This feature helps to implement M_NO_START 22*4882a593Smuzhiyun as per I2C core API transfer flags. Driver of I2C controller is 23*4882a593Smuzhiyun compatible with "nvidia,tegra30-i2c" to enable the continue transfer 24*4882a593Smuzhiyun support. This is also compatible with "nvidia,tegra20-i2c" without 25*4882a593Smuzhiyun continue transfer support. 26*4882a593Smuzhiyun nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is 27*4882a593Smuzhiyun very much similar to Tegra30 I2C controller with some hardware 28*4882a593Smuzhiyun modification: 29*4882a593Smuzhiyun - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and 30*4882a593Smuzhiyun fast-clk. Tegra114 has only one clock source called as div-clk and 31*4882a593Smuzhiyun hence clock mechanism is changed in I2C controller. 32*4882a593Smuzhiyun - Tegra30/Tegra20 I2C controller has enabled per packet transfer by 33*4882a593Smuzhiyun default and there is no way to disable it. Tegra114 has this 34*4882a593Smuzhiyun interrupt disable by default and SW need to enable explicitly. 35*4882a593Smuzhiyun Due to above changes, Tegra114 I2C driver makes incompatible with 36*4882a593Smuzhiyun previous hardware driver. Hence, tegra114 I2C controller is compatible 37*4882a593Smuzhiyun with "nvidia,tegra114-i2c". 38*4882a593Smuzhiyun nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus 39*4882a593Smuzhiyun and is part of VE power domain and typically used for camera use-cases. 40*4882a593Smuzhiyun This VI I2C controller is mostly compatible with the programming model 41*4882a593Smuzhiyun of the regular I2C controllers with a few exceptions. The I2C registers 42*4882a593Smuzhiyun start at an offset of 0xc00 (instead of 0), registers are 16 bytes 43*4882a593Smuzhiyun apart (rather than 4) and the controller does not support slave mode. 44*4882a593Smuzhiyun- reg: Should contain I2C controller registers physical address and length. 45*4882a593Smuzhiyun- interrupts: Should contain I2C controller interrupts. 46*4882a593Smuzhiyun- address-cells: Address cells for I2C device address. 47*4882a593Smuzhiyun- size-cells: Size of the I2C device address. 48*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 49*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 50*4882a593Smuzhiyun- clock-names: Must include the following entries: 51*4882a593Smuzhiyun Tegra20/Tegra30: 52*4882a593Smuzhiyun - div-clk 53*4882a593Smuzhiyun - fast-clk 54*4882a593Smuzhiyun Tegra114: 55*4882a593Smuzhiyun - div-clk 56*4882a593Smuzhiyun Tegra210: 57*4882a593Smuzhiyun - div-clk 58*4882a593Smuzhiyun - slow (only for nvidia,tegra210-i2c-vi compatible node) 59*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 60*4882a593Smuzhiyun See ../reset/reset.txt for details. 61*4882a593Smuzhiyun- reset-names: Must include the following entries: 62*4882a593Smuzhiyun - i2c 63*4882a593Smuzhiyun- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must 64*4882a593Smuzhiyun include venc powergate node as vi i2c is part of VE power domain. 65*4882a593Smuzhiyun tegra210-i2c-vi: 66*4882a593Smuzhiyun - pd_venc 67*4882a593Smuzhiyun- dmas: Must contain an entry for each entry in clock-names. 68*4882a593Smuzhiyun See ../dma/dma.txt for details. 69*4882a593Smuzhiyun- dma-names: Must include the following entries: 70*4882a593Smuzhiyun - rx 71*4882a593Smuzhiyun - tx 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunExample: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun i2c@7000c000 { 76*4882a593Smuzhiyun compatible = "nvidia,tegra20-i2c"; 77*4882a593Smuzhiyun reg = <0x7000c000 0x100>; 78*4882a593Smuzhiyun interrupts = <0 38 0x04>; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <0>; 81*4882a593Smuzhiyun clocks = <&tegra_car 12>, <&tegra_car 124>; 82*4882a593Smuzhiyun clock-names = "div-clk", "fast-clk"; 83*4882a593Smuzhiyun resets = <&tegra_car 12>; 84*4882a593Smuzhiyun reset-names = "i2c"; 85*4882a593Smuzhiyun dmas = <&apbdma 16>, <&apbdma 16>; 86*4882a593Smuzhiyun dma-names = "rx", "tx"; 87*4882a593Smuzhiyun }; 88