1*4882a593SmuzhiyunDevice tree configuration for the Mellanox I2C SMBus on BlueField SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2". 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg : address offset and length of the device registers. The 8*4882a593Smuzhiyun registers consist of the following set of resources: 9*4882a593Smuzhiyun 1) Smbus block registers. 10*4882a593Smuzhiyun 2) Cause master registers. 11*4882a593Smuzhiyun 3) Cause slave registers. 12*4882a593Smuzhiyun 4) Cause coalesce registers (if compatible isn't set 13*4882a593Smuzhiyun to "mellanox,i2c-mlxbf1"). 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- interrupts : interrupt number. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional Properties: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- clock-frequency : bus frequency used to configure timing registers; 20*4882a593Smuzhiyun allowed values are 100000, 400000 and 1000000; 21*4882a593Smuzhiyun those are expressed in Hz. Default is 100000. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyuni2c@2804000 { 26*4882a593Smuzhiyun compatible = "mellanox,i2c-mlxbf1"; 27*4882a593Smuzhiyun reg = <0x02804000 0x800>, 28*4882a593Smuzhiyun <0x02801200 0x020>, 29*4882a593Smuzhiyun <0x02801260 0x020>; 30*4882a593Smuzhiyun interrupts = <57>; 31*4882a593Smuzhiyun clock-frequency = <100000>; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyuni2c@2808800 { 35*4882a593Smuzhiyun compatible = "mellanox,i2c-mlxbf2"; 36*4882a593Smuzhiyun reg = <0x02808800 0x600>, 37*4882a593Smuzhiyun <0x02808e00 0x020>, 38*4882a593Smuzhiyun <0x02808e20 0x020>, 39*4882a593Smuzhiyun <0x02808e40 0x010>; 40*4882a593Smuzhiyun interrupts = <57>; 41*4882a593Smuzhiyun clock-frequency = <400000>; 42*4882a593Smuzhiyun}; 43