1*4882a593SmuzhiyunQualcomm Camera Control Interface (CCI) I2C controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPROPERTIES: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun Usage: required 7*4882a593Smuzhiyun Value type: <string> 8*4882a593Smuzhiyun Definition: must be one of: 9*4882a593Smuzhiyun "qcom,msm8916-cci" 10*4882a593Smuzhiyun "qcom,msm8996-cci" 11*4882a593Smuzhiyun "qcom,sdm845-cci" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- reg 14*4882a593Smuzhiyun Usage: required 15*4882a593Smuzhiyun Value type: <prop-encoded-array> 16*4882a593Smuzhiyun Definition: base address CCI I2C controller and length of memory 17*4882a593Smuzhiyun mapped region. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- interrupts: 20*4882a593Smuzhiyun Usage: required 21*4882a593Smuzhiyun Value type: <prop-encoded-array> 22*4882a593Smuzhiyun Definition: specifies the CCI I2C interrupt. The format of the 23*4882a593Smuzhiyun specifier is defined by the binding document describing 24*4882a593Smuzhiyun the node's interrupt parent. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- clocks: 27*4882a593Smuzhiyun Usage: required 28*4882a593Smuzhiyun Value type: <prop-encoded-array> 29*4882a593Smuzhiyun Definition: a list of phandle, should contain an entry for each 30*4882a593Smuzhiyun entries in clock-names. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- clock-names 33*4882a593Smuzhiyun Usage: required 34*4882a593Smuzhiyun Value type: <string> 35*4882a593Smuzhiyun Definition: a list of clock names, must include "cci" clock. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- power-domains 38*4882a593Smuzhiyun Usage: required for "qcom,msm8996-cci" 39*4882a593Smuzhiyun Value type: <prop-encoded-array> 40*4882a593Smuzhiyun Definition: 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunSUBNODES: 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunThe CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and 45*4882a593Smuzhiyunsdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunPROPERTIES: 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun- reg: 50*4882a593Smuzhiyun Usage: required 51*4882a593Smuzhiyun Value type: <u32> 52*4882a593Smuzhiyun Definition: Index of the CCI bus/master 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- clock-frequency: 55*4882a593Smuzhiyun Usage: optional 56*4882a593Smuzhiyun Value type: <u32> 57*4882a593Smuzhiyun Definition: Desired I2C bus clock frequency in Hz, defaults to 100 58*4882a593Smuzhiyun kHz if omitted. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunExample: 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun cci@a0c000 { 63*4882a593Smuzhiyun compatible = "qcom,msm8996-cci"; 64*4882a593Smuzhiyun #address-cells = <1>; 65*4882a593Smuzhiyun #size-cells = <0>; 66*4882a593Smuzhiyun reg = <0xa0c000 0x1000>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 68*4882a593Smuzhiyun clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, 69*4882a593Smuzhiyun <&mmcc CAMSS_TOP_AHB_CLK>, 70*4882a593Smuzhiyun <&mmcc CAMSS_CCI_AHB_CLK>, 71*4882a593Smuzhiyun <&mmcc CAMSS_CCI_CLK>, 72*4882a593Smuzhiyun <&mmcc CAMSS_AHB_CLK>; 73*4882a593Smuzhiyun clock-names = "mmss_mmagic_ahb", 74*4882a593Smuzhiyun "camss_top_ahb", 75*4882a593Smuzhiyun "cci_ahb", 76*4882a593Smuzhiyun "cci", 77*4882a593Smuzhiyun "camss_ahb"; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun i2c-bus@0 { 80*4882a593Smuzhiyun reg = <0>; 81*4882a593Smuzhiyun clock-frequency = <400000>; 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun i2c-bus@1 { 87*4882a593Smuzhiyun reg = <1>; 88*4882a593Smuzhiyun clock-frequency = <400000>; 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93