1*4882a593SmuzhiyunCE4100 I2C 2*4882a593Smuzhiyun---------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunCE4100 has one PCI device which is described as the I2C-Controller. This 5*4882a593SmuzhiyunPCI device has three PCI-bars, each bar contains a complete I2C 6*4882a593Smuzhiyuncontroller. So we have a total of three independent I2C-Controllers 7*4882a593Smuzhiyunwhich share only an interrupt line. 8*4882a593SmuzhiyunThe driver is probed via the PCI-ID and is gathering the information of 9*4882a593Smuzhiyunattached devices from the devices tree. 10*4882a593SmuzhiyunGrant Likely recommended to use the ranges property to map the PCI-Bar 11*4882a593Smuzhiyunnumber to its physical address and to use this to find the child nodes 12*4882a593Smuzhiyunof the specific I2C controller. This were his exact words: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun Here's where the magic happens. Each entry in 15*4882a593Smuzhiyun ranges describes how the parent pci address space 16*4882a593Smuzhiyun (middle group of 3) is translated to the local 17*4882a593Smuzhiyun address space (first group of 2) and the size of 18*4882a593Smuzhiyun each range (last cell). In this particular case, 19*4882a593Smuzhiyun the first cell of the local address is chosen to be 20*4882a593Smuzhiyun 1:1 mapped to the BARs, and the second is the 21*4882a593Smuzhiyun offset from be base of the BAR (which would be 22*4882a593Smuzhiyun non-zero if you had 2 or more devices mapped off 23*4882a593Smuzhiyun the same BAR) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ranges allows the address mapping to be described 26*4882a593Smuzhiyun in a way that the OS can interpret without 27*4882a593Smuzhiyun requiring custom device driver code. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThis is an example which is used on FalconFalls: 30*4882a593Smuzhiyun------------------------------------------------ 31*4882a593Smuzhiyun i2c-controller@b,2 { 32*4882a593Smuzhiyun #address-cells = <2>; 33*4882a593Smuzhiyun #size-cells = <1>; 34*4882a593Smuzhiyun compatible = "pci8086,2e68.2", 35*4882a593Smuzhiyun "pci8086,2e68", 36*4882a593Smuzhiyun "pciclass,ff0000", 37*4882a593Smuzhiyun "pciclass,ff00"; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun reg = <0x15a00 0x0 0x0 0x0 0x0>; 40*4882a593Smuzhiyun interrupts = <16 1>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* as described by Grant, the first number in the group of 43*4882a593Smuzhiyun * three is the bar number followed by the 64bit bar address 44*4882a593Smuzhiyun * followed by size of the mapping. The bar address 45*4882a593Smuzhiyun * requires also a valid translation in parents ranges 46*4882a593Smuzhiyun * property. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun ranges = <0 0 0x02000000 0 0xdffe0500 0x100 49*4882a593Smuzhiyun 1 0 0x02000000 0 0xdffe0600 0x100 50*4882a593Smuzhiyun 2 0 0x02000000 0 0xdffe0700 0x100>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun i2c@0 { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun compatible = "intel,ce4100-i2c-controller"; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* The first number in the reg property is the 58*4882a593Smuzhiyun * number of the bar 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun reg = <0 0 0x100>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* This I2C controller has no devices */ 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun i2c@1 { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun compatible = "intel,ce4100-i2c-controller"; 69*4882a593Smuzhiyun reg = <1 0 0x100>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* This I2C controller has one gpio controller */ 72*4882a593Smuzhiyun gpio@26 { 73*4882a593Smuzhiyun #gpio-cells = <2>; 74*4882a593Smuzhiyun compatible = "ti,pcf8575"; 75*4882a593Smuzhiyun reg = <0x26>; 76*4882a593Smuzhiyun gpio-controller; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun i2c@2 { 81*4882a593Smuzhiyun #address-cells = <1>; 82*4882a593Smuzhiyun #size-cells = <0>; 83*4882a593Smuzhiyun compatible = "intel,ce4100-i2c-controller"; 84*4882a593Smuzhiyun reg = <2 0 0x100>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun gpio@26 { 87*4882a593Smuzhiyun #gpio-cells = <2>; 88*4882a593Smuzhiyun compatible = "ti,pcf8575"; 89*4882a593Smuzhiyun reg = <0x26>; 90*4882a593Smuzhiyun gpio-controller; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94