1*4882a593Smuzhiyun* NXP PNX I2C Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - reg: Offset and length of the register set for the device 6*4882a593Smuzhiyun - compatible: should be "nxp,pnx-i2c" 7*4882a593Smuzhiyun - interrupts: configure one interrupt line 8*4882a593Smuzhiyun - #address-cells: always 1 (for i2c addresses) 9*4882a593Smuzhiyun - #size-cells: always 0 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional properties: 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExamples: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun i2c1: i2c@400a0000 { 18*4882a593Smuzhiyun compatible = "nxp,pnx-i2c"; 19*4882a593Smuzhiyun reg = <0x400a0000 0x100>; 20*4882a593Smuzhiyun interrupt-parent = <&mic>; 21*4882a593Smuzhiyun interrupts = <51 0>; 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <0>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun i2c2: i2c@400a8000 { 27*4882a593Smuzhiyun compatible = "nxp,pnx-i2c"; 28*4882a593Smuzhiyun reg = <0x400a8000 0x100>; 29*4882a593Smuzhiyun interrupt-parent = <&mic>; 30*4882a593Smuzhiyun interrupts = <50 0>; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <0>; 33*4882a593Smuzhiyun clock-frequency = <100000>; 34*4882a593Smuzhiyun }; 35