1*4882a593Smuzhiyun* Two Wire Serial Interface (TWSI) / I2C 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun- compatible: "cavium,octeon-3860-twsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun or 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun compatible: "cavium,octeon-7890-twsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun Compatibility with cn78XX SOCs. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- reg: The base address of the TWSI/I2C bus controller register bank. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #address-cells: Must be <1>. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- #size-cells: Must be <0>. I2C addresses have no size component. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- interrupts: A single interrupt specifier. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- clock-frequency: The I2C bus clock rate in Hz. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun twsi0: i2c@1180000001000 { 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun compatible = "cavium,octeon-3860-twsi"; 28*4882a593Smuzhiyun reg = <0x11800 0x00001000 0x0 0x200>; 29*4882a593Smuzhiyun interrupts = <0 45>; 30*4882a593Smuzhiyun clock-frequency = <100000>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun rtc@68 { 33*4882a593Smuzhiyun compatible = "dallas,ds1337"; 34*4882a593Smuzhiyun reg = <0x68>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun tmp@4c { 37*4882a593Smuzhiyun compatible = "ti,tmp421"; 38*4882a593Smuzhiyun reg = <0x4c>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41